Basic Circuit Concepts

Introduction
Wiring-Up of chip devices takes place through various conductors produced during processing Today, interconnects constitute the main source of delay in MOS circuits We will examine:
Sheet Resistance Resistance / Unit Area Area Capacitance Delay Units CMOS Inverter Delay Rise and Fall Time Estimation

Sheet Resistance
Resistance of a square slab of material RAB = L/A t => R = L/t*W Let L = W (square slab) => RAB = /t = Rs ohm / square
A w

B
RAB = ZRsh Z = L/W

Typical sheet resistance values for materials are very well characterised

Layer
Aluminium N Diffusion Silicide Polysilicon N-transistor Channel

Rs (Ohm / Sq)
0.03 10 50 24 15 - 100 104

P-transistor Channel

2.5 x 104

Typical Sheet Resistances for 5m Technology

N-type Minimum Feature Device

Polysilicon N - diffusion L

2 R = 1sq x Rs = Rs = 104

Polysilicon

W = 8

L = 2

N - diffusion R = Z Rs R = (L/W) * Rs R = 4*104

Area Capacitance of Layers

Conducting layers are separated from each other by insulators (typically SiO2) This may constitute a parallel plate capacitor, C = 0r(ox) A / D (farads) D = thickness of oxide, A = area, ox = 4 F/m2 Area capacitance given in pF/m2

Capacitance
Standard unit for a technology node is the gate - channel capacitance of the minimum sized transistor (2 x 2), given as Cg This is a technology specific value
For 5m technology, Cg = 0.01pF/m2

Delay Unit
For a feature size square gate, = Rs x Cg i.e for 5m technology, = 104 ohm/sq x 0.01pF = 0.1ns Because of effects of parasitics which we have not considered in our model, delay is typically of the order of 0.2 - 0.3 ns Note that is very similar to channel transit time sd

CMOS Inverter Delay

Pull-down delay = Rpd x 2 Cg Pull-up delay = Rpu x 2 Cg Asymmetry in rise and fall due to resistance difference between pull-up and pull-down (factor of 2.5) (due to mobilities of carriers) Delay through a pair of inverters is 2 (fall time) + 5 (rise time) Delay through a pair of CMOS inverters is therefore 7

CMOS Inverter Delay

Asymmetry can be improved by reducing resistance of pull - up Reduce resistance of pull - up by increasing channel width ( typically by a factor of 2.5) Note that increasing channel width also increases the capacitance The overall delay (after increasing channel width by 2.5) will be the same 7

CMOS Inverter Rise and Fall Time Estimation

Tf ~ 3CL / KnVDD r ~ 3CL / KpVDD (Derivations for the above are in Pucknell and Eshraghian Pages 105 - 107) So, r/ f = Kn/Kp Given that (due to mobilities) Kn = 2.5 Kp, rise time is slower by a factor of 2.5 when using minimum dimensions of n and p transistors