Sie sind auf Seite 1von 66

Outline

Conventional System Design Methodology ASIC/VLSI Design methodology - Logic Design - Physical Design - Fabrication Conclusion

PCB Product Design Methodology


Specification
Various Technologies

Architecture Design Logic Design Physical Design Product Assembly Test Production Product

System Block Diagram

I N P U T

System

o U T P U T

Control

System Block Diagram


comp PLA I/O

I N P U T

RAM

System

A/D

o U T P U T

Control

Logic Design

Physical Design -Layout

Components for Assembly

Product
Logic gates & Components

nets

IO Ports substrate

Test
Functional Design Parameters Environmental Reliability

Miniaturization & Integration

ASIC PCB Product

Overview of VLSI Design Methodology


Specification

VLSI Technology

ASIC

ASIC/VLSI Design Methodology


Specification
Various Technologies

crosstalk Analysis

Architecture Design
Timing Analysis

System Simulation Logic Verification


Physical Verification Extrapolated verification Electrical Testing Quality Assurance

Power Analysis

Logic Design Physical Design Fabrication Test Production Product - ASIC

Environmental Testing Reliability Testing

Functional Parameters Performance/Design Parameters -- Area -- Speed -- Power -- Noise Technology -- Complexity/Density -- Design Turnaround Time -- Design Methodology -- EDA Tools -- Process Technology -- Library -- Operating Conditions -- Cost

System Design Parameters

Moores Law
Microprocessors
PPC603 Pentium 80486 Pentium Pro PPC601 MIPS R4000 68040

10M

Transistors

1M
4004

80386 68020 68000 8086 8080

100K 10K 1K 100 10 1

17

Technology : Die SIZES


Silicon Process 1.5m Technology Intel386TM DX Processor Intel486TM DX Processor Pentium Processor Pentium Pro & Pentium II Processors 1.0m 0.8m 0.6m 0.35m 0.25m
Fall 2003

18

EE 5301 - VLSI Design Automation I

Functionality

Functionality & Technology Gate


Density

Technology

EDA Tools
Results (design productivity) Whats next?

Synthesis Cadence, Synopsys Schematic entry Daisy, Mentor, Valid Transistor entry Calma, Computervision, Magic

Effort 20 (EDA tool effort)

Design Abstraction
Algorithmic
Effectiveness

Gate-level
Reduce fan-out, capacitance Gate duplication, buffer insertion

Layout / Physical-Design
Move cells/gates around to shorten wires on critical

Level of detail
21

Encoding data, computation scheduling, balancing delays of components, etc.

Behavioral Domain Application algorithms

Design Methodologies Y Chart Synthesis


Structural Domain

processors
ALUs , registers Logic gates

programs Subroutines ,B.equations instructions

Transistors

Layout transistor Cells Chips / modules Circuit abstraction level Chips.MCM,boards Micro architecture abstraction level

Logic abstraction level

System abstractio level

Physical domain

ASIC Design Styles


Design Methods
Full Custom Standard Cell Cost / Development Time Quality # Companies involved

Gate Array

FPGA

23

A Typical ASIC Design Flow


Specification

LOGIC DESIGN PHYSICAL DESIGN Foundry

Technologies

ASIC

Logic Design Methodology Customer


Specification Architectural Design Logic Simulation Logic Synthesis

Structural Design

Logical Library

Bug Free RTL Code Gate Level Netlist

Std. Cells Macros IO Cells

System Architecture
memwrite memread

controller

aluop[1:0]

alucontrol
funct[5:0]
alucontrol[2:0]

op[5:0]

zero

alusrca

alusrcb[1:0]

pcen

pcsource[1:0]

memtoreg

regdst

iord

regwrite

irwrite[3:0]

ph1 ph2 reset adr[7:0] writedata[7:0] memdata[7:0]

datapath

Design Hierarchy
Processor controller ALU Arithmetic Data Path

Logic

Sequencing

Divider

Full Adder
Half Adder

Multiplier

Half Adder

XOR

AND

XOR

AND

AND

OR

INV

AND

OR

INV

ALU : Block Level

ALU : Gate Level

ALU Operations OP OP OP OP = = = = 000 001 010 011 XOR AND OR Addition

Full Adder : Block Level


a b c a cout s f ulladder cout s b c carry sum

Full Adder using half Adder

Logic : Gate Level/Structural Model Structural :


g1 a b
A B C

x g2 g4 y g3 z cout

a c
S= A+B+C

b c

Behavioral : assign cout = (a&b) | (a&c) | (b&c);

Full Adder : Behavioral Model Design


module fulladder(input a, b, c, output s, cout); sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule

module carry(input a, b, c, output cout)

Carry : Gate Level Netlist


module carry(input a, b, c, output cout) wire x, y, z; b); c); c); x, y, z);

and g1(x, a, and g2(y, a, and g3(z, b, or g4(cout, endmodule

Logic Simulation thru Test Bench


TEST BENCH

I N P U T

Design

O U T P U T

CONTROL VECTORS

Test Bench using HDL


Test Bench
module main; reg a, b; wire sum, carry; halfadder add(a,b,sum,carry); always @(sum or carry) begin $display("time=%d:%b + %b = %b, carry = %b\n",$time,a,b,sum,carry); end initial begin a = 0; b = 0; #5 a = 0; b = 1; #5 a = 1; b = 0; #5 a = 1; b = 1; end endmodule

Functional Verification

Logic & Physical Library


Logic INV A B INV V d d Physical NAND V d d A Y Y NOR V s s B V s s NOR V d d

A NAND B

A
Y

A Y B V s s

Targeted Technology Library Parameters Types of Libraries : Area Optimized


Power Optimized Timing Optimized Parameter Limit : Min, Typ , Max Parameters Types Electrical : VDD (max/min) , V ol/oh, V ol/ih etc Thermal : Defense, Industrial, Consumer Timing : tp hl/hl, tr, tf , ts, th etc Process : Stringent, Typical, Leanient

Library Components : Std.Cell around 400 Types various Drive Strengths - INV,NAND,AOI,FF,MUX,LATCHES etc Macros PLL,RAM,ROM,ADC etc IO Cells VDD,VSS, Clk, Data Bus etc.

Synthesis to Library
RTL Code

Synthesis Translation
Optimization Mapping Gate Level Netlist

Technology Logic Library


IO Cell Macros Std. Cell

What is Synthesis? Logic Synthesis is the automated process of converting a functional model of a system into a gate-level circuit.

Why Synthesis is required?


Benefits of synthesis: High level design entry Increased designer productivity Reduction of layout design expertise requirement Improved quality Technology independence Facilitates design re-use and sharing

SYNTHESIS = TRANSLATION + OPTIMIZATION + MAPPING

HDL Source

+ Mapping Generic ( GTECH)

Target Technology

Synthesis Flow

AND GATE
SYNTHESIS = TRANSILATION + OPTIMIZATION + MAPPING module and2 (z, a, b); output z; input a, b; always @ (a or b) if (a == 1 and b == 1) z <= 1; else z <= 0; endmodule a z b

OR GATE
TRANSILATION module or2 (z, a, b); output z; input a, b; a z b

always @ (a or b) if (a == 0 and b == 0) z <= 0; else z <= 1;


endmodule

OPTIMIZATION a z b

D-FLIP FLOP
module cnt (q, d, clk, rst);
output q; input d, clk, rst; reg q; always @ (posedge clk) if (rst) q <= 0; else q <= d; endmodule

module cnt (q, d, clk, rst);


output q; input d, clk, rst; reg q; always @ (posedge clk or posedge rst) if (rst) q <= 0; else q <= d; endmodule

COUNTER
module cnt (cout, clk, rst);
output [3:0] cout; input clk, rst; reg [3:0] cout; 0 always @ (posedge clk) if (rst) cout <= 4b0; else cout <= cout + 1b1; endmodule 0 1 clk 4 d q 4
+1

rst

Code for Synthesis


Code that is functionally equivalent, but coded differently, will give different synthesis results.

You cannot rely solely on Tool to fix a poorly coded design. Try to understand the hardware you are describing, to give tool the best possible starting point.

Order and Group Arithmetic Functions The ordering and grouping of arithmetic functions can influence design performance. For Verilog, the following two statements are not necessarily equivalent. Statement1: ADD = A1 + A2 + A3 + A4; Statement2: ADD = (A1 + A2) + (A3 + A4); The second statement creates two adders in parallel: A1 + A2 and A3 + A4. In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder. RTL simulation results are the same for both statements, however, the second statement results in a faster circuit after synthesis (depending on the bit width of the input signals).

Statement1: ADD = A1 + A2 + A3 + A4;

The first statement cascades three adders in series.

Statement2: ADD = (A1 + A2) + (A3 + A4);

In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder.

Resource Sharing
Resource sharing is an optimization technique that uses a single functional block (such as an adder or comparator) to implement several operators in the HDL code. Use resource sharing to improve design performance by reducing the gate count and the routing congestion. If you do not use resource sharing, each HDL operation is built with separate circuitry. However, you may want to disable resource sharing for speed critical paths in your design.

Resource Sharing

Resource Sharing

Mapping
High-level synthesis is Constraint-Driven. High-level synthesis is based on design constraints and coding style Tool makes high-level synthesis decisions to produce areaefficient results that meet timing. High-level Synthesis takes place only when optimizing an unmapped design

It will not occur when re-optimizing a gate-level netlist.


Exception: Incremental implementation selection can recur after mapping to gates.

Combinational mapping

Order and Group Arithmetic Functions

Order and Group Arithmetic Functions


Although the second statement generally results in a faster circuit, in some cases, you may want to use the first statement. For example, if the A4 signal reaches the adder later than the other signals, the first statement produces a faster implementation because the cascaded structure creates fewer logic levels for A4. This structure allows A4 to catch up to the other signals. In this case, A1 is the fastest signal followed by A2 and A3; A4 is the slowest signal. Most synthesis tools can balance or restructure the arithmetic operator tree if timing constraints require it. However, it is recommended that you code your design for your selected structure.

Multiple Architectures for each Macro

Ripple Carry

Ripple Carry-Select

+
Carry Look Ahead

Carry Save

Synthesis Input : RTL Code


Design

module Halfadder (a,b,sum,carry); input a,b; output sum, carry; wire sum, carry; assign sum = a^b; // sum bit assign carry = (a&b) ;//carry bit endmodule

Translation/Optimization - Gentech
Algorithmic . S = A XOR B = A. B + A. B C = A AND B = A . B

Schematic

Mapped to Generic Library


Design : Generic

A u1 u2 B D

u3 E

u4
S

Mapped to Technology
Design: Technology Mapped
Technology Library NOT Gate ANDL AND2L AND4L ANDXL
A N D 2L N O T L

A u1

u2 B
O R 2L

u3 E
A N D 4L

u4
S

OR Gate ORL OR2L OR4L ORXL AND Gate ANDL AND2L AND4L ANDXL AOI Gate --------

Synthesized Gate Level Netlist


Module Half Adder S, C, A, B ;

AND2L OR2L NOTL AND4L --Gates

u1 u2 u3 u4 -

S A B ; D A B ; E S ; C D E ; -----

nets

End Module
instantiation