Programming Language Interface (PLI)

Pedram A. Riahi Test Seminar August 11th, 2004

Contents
PLI History Verilog PLI Overview Verilog VPI Routines Cadence VPI Environment Mentor Graphics VPI Environment References

Aug. 11th, 2004

Test Seminar

PLI History

1985 - The PLI was developed by Gateway Design Automation as part of the proprietary Verilog-XL simulator 1990 - The PLI standard was released to the public domain along with the Verilog HDL and Verilog SDF standards by Cadence Design System 1990 - Open Verilog International (OVI) owned the Verilog HDL, the OVI version of the PLI was called PLI 1.0 1993 - OVI released PLI 2.0, a completely new interface, intended to replace PLI 1.0 1993 - OVI submitted Verilog to the IEEE for standardization 1995 -The IEEE-1364-1995 Verilog PLI standard was released 2001 -The IEEE-1364-2001 Verilog HDL & PLI standard updated with many new language features many new language features

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Test Seminar

Verilog PLI Overview

IEEE Std Verilog HDL LRM Clauses 20-27 and Appendices E-G Verilog PLI Generations:

Task/Function Routines (TF Routines, tf_) Access Routines (ACC Routines, acc_) Verilog Procedural Interface Routines (VPI Routines, vpi_)

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Test Seminar

Verilog PLI Overview

User-Defined System Tasks and Functions

Names ($) Types Overriding User-Supplied PLI Applications Arguments

Interface Mechanism Include Files

acc_user.h veriuser.h vpi_user.h

Memory Restriction

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Test Seminar

Verilog VPI Routines

System Tasks and Functions

vpi_register_systf() vlog_startup_routines[]

Interface

Call-backs

vpi_register_cb()

Access to HDL and Simulation Objects

module m, wire w: m1.w, m2.w

Error Handling Function Availability Traversing Expressions

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Test Seminar

Verilog VPI Routines

Call-backs

Simulation Call-backs
Simulation Action and Features Simulation Times Simulation Events

Statement Call-backs Removing Call-backs

Time Queue

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Verilog VPI Routines

Diagram Key for Objects and Classes

Object Definition
Object Reference

Class Definition

Class Reference

Unnamed Class

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Test Seminar

Verilog VPI Routines

Diagram Key for Traversing Relationships

obj_h = vpi_handle (obj, ref_h);

obj_h = vpi_handle (Tag, ref_h);

obj_h = vpi_handle (obj, NULL);

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Test Seminar

Verilog VPI Routines

Diagram Key for Traversing Relationships

itr = vpi_iterate (obj, ref_h); while (obj_h = vpi_scan (itr)) { process obj_h}

itr = vpi_iterate (Tag, ref_h); while (obj_h = vpi_scan (itr)) { process obj_h}

itr = vpi_iterate (obj, NULL); while (obj_h = vpi_scan (itr)) { process obj_h}

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Verilog VPI Routines

Diagram Key for Accessing Properties

PLI_INT32 vect_flag = vpi_get (vpiVector, obj_h); PLI_INT32 size = vpi_get (vpiSize, obj_h); PLI_INT8 *name = vpi_get_str (vpiName, obj_h);

Identified Routines

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Verilog VPI Routines

Object Relationships and Properties

modH = vpi_handle (vpiModule, netH);

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Verilog VPI Routines

Object Relationships and Properties

vpiHandle net, mod; net = vpiHandle_by_name (top.m1.w, NULL); mod = vpi_handle (vpiModule, net);

vpi_handle (vpiExpr, partH);

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Verilog VPI Routines

Object Relationships and Properties

PLI_BYTE8 *name = vpi_get_str (vpiFullName, mod);

vpiHandle itr; itr = vpi_iterate(vpiNet, mod); while (net = vpi_scan (itr)) vpi_printf(%s\n, vpi_get_str (vpiFullName, net));

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Verilog VPI Routines

Object Relationships and Properties

void traverseExpr (vpiHandle expr) { vpiHandle subExprI, subExprH; switch (vpi_get (vpiExpr, expr)) { case vpiOperation: subExprI = vpi_iterate (vpiOperand, expr); if (subExprI) while (subExprH = vpi_scan (subExprI)) traverseExpr (subExprH); default: break; }}

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Verilog VPI Routines

Object Relationships and Properties

Type Properties -> type int: vpiType

vpi_get (vpiType, H); vpi_get_str (vpiType, H);

File and -> location int: vpiLineNo str: vpiFile

Line Properties

Delays and Values

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Test Seminar

Verilog VPI Routines

VPI Routines for Simulation Related Call-backs

vpi_register_cb(): Register a simulation-related call-back vpi_remove_cb(): Remove a simulation-related call-back vpi_get_cb_info(): Get information about a simulation-related call-back

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Verilog VPI Routines

VPI Routines for System Task/Function Call-backs

vpi_register_systf(): Register a system task/function call-back vpi_get_systf_info(): Get information about a system task/function call-back

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Verilog VPI Routines

VPI Routines for Traversing Verilog HDL Hierarchy

vpi_handle(): Obtain a handle for an object with a one-to-one relationship vpi_iterate(), vpi_scan(): Obtain handles for objects in a one-to-many relationship vpi_handle_multi(): Obtain a handle for an object in a many-to-one relationship

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Verilog VPI Routines

VPI Routines for Accessing Properties of Objects

vpi_get(): Get the value of objects with types of int or bool vpi_get_str(): Get the value of objects with types of string

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Verilog VPI Routines

VPI Routines for Accessing Objects from Properties

vpi_handle_by_name(): Obtain a handle for a named object vpi_handle_by_index(): Obtain a handle for an indexed object vpi_handle_by_multi_index(): Obtain a handle to a word or bit in an array

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Verilog VPI Routines

VPI Routines for Delay Processing

vpi_get_delays(): Retrieve delays or timing limits of an object vpi_put_delays(): Write delays or timing limits to an object

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Verilog VPI Routines

VPI Routines for Logic and Strength Value Processing

vpi_get_value(): Retrieve logic value or strength value of an object vpi_put_value(): Write logic value or strength value to an object

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Verilog VPI Routines

VPI Routines for Simulation Time Processing

vpi_get_time(): Find the current simulation time or the scheduled time of future events

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Verilog VPI Routines

VPI Routines for Miscellaneous Utilities

vpi_printf() vpi_vprintf() vpi_flush() vpi_mcd_open() vpi_mcd_close() vpi_mcd_printf() vpi_mcd_vprintf() vpi_mcd_flush() vpi_mcd_name() vpi_get_vlog_info() vpi_compare_objects() vpi_chk_error() vpi_free_object() vpi_put_data() vpi_get_data() vpi_put_userdata() vpi_get_userdata() vpi_sim_control()

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Verilog VPI Routines

Module Data Model

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Verilog VPI Routines

Net Data Model

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Verilog VPI Routines

Reg Data Model

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Verilog VPI Routines

Cadence PLI Environment

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Verilog VPI Routines

Cadence PLI Environment

Creating a C Function

#include <stdio.h> #include vpi_user.h int hello_task () { vpi_printf (Hello from a new VPI task \n);}

Creating a C++ Function

extern C void ncmain (int, char **); main(argc, argv) int argc; char* argv[]; { ncmain(argc, argv); }

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Verilog VPI Routines

Cadence PLI Environment

Associating C Function with a new System Task

void register_my_systfs () { s_vpi_systf_data task_data_s; p_vpi_systf_data task_data_p = &task_data_s; task_data_p->type = vpiSysTask; task_data_p->tfname = $hello ; task_data_p->calltf = (int(*)()) hello_task; task_data_p->compiletf = NULL; vpi_register_systf (task_data_p); }

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Verilog VPI Routines

Cadence PLI Environment

Registering Users New System Task

/* vpi_user.c */ #include vpi_user.h #include vpi_user_cds.h void (*vlog_startup_routines[]) () = {register_my_systfs, 0};

Invoking Users System Task

module top; Initial begin $hello; end endmodule

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Verilog VPI Routines

Cadence PLI Environment

Compiling C Files (vconfig)

Static/Dynamic

cc -KPIC -c ~/vpi_user.c -I<InstDir>/include cc -KPIC -c ~/hello.c -I<InstDir>/include ld -G vpi_user.o hello.o -o libvpi.so executable file

Compiling and Simulating Verilog File

setenv LD_LIBRARY_PATH \ ~/<LibDir>:$LD_LIBRARY_PATH ncelab access+rwc worklib.top:v ncverilog +ncaccess+rwc +plinowarn hello.v

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Verilog VPI Routines

Mentor Graphics PLI Environment

Compiling C Files

cc -c ~/vpi_user.c -I<InstDir>/include cc -c ~/hello.c -I<InstDir>/include ld -G vpi_user.o hello.o -o vpi_lib.so

Compiling and Simulating Verilog File (modelsim.ini)

vlib work vlog hello.v vsim -c -pli vpi_lib.so top

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References
Cadence Design Systems, Inc., VPI User Guide and Reference, Product Version 3.2, Dec. 2000. Cadence Design Systems, Inc., NCVerilog Simulator Help, Product Version 3.2, Dec. 2000. Cadence Design Systems, Inc., Verilog-XL User Guide and Reference, Product Version 2.8, Aug. 1999. Mentor Graphics, ModelSim SE User's Manual, Version 5.7a, Jan. 2003 Stuart Sutherland, The Verilog PLI Handbook, Kluwer Academic Publishers, 2002. Swapnajit Mittra, Principles of Verilog PLI, Kluwer Academic Publishers, 1999.

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