EEN1036 Digital Logic Design

Chapter 3 part II Combinational Logic Circuit

Objective

Implement circuit from Boolean expressions Describing logic circuits algebraically From truth table to logic circuit Evaluating logic circuit outputs Implement logic circuits using only NAND and NOR gates Deriving output waveform for a given timing diagram
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Introduction
The relationship between Boolean expression, truth table and logic circuit is as shown below:
SOP/ POS Boolean expression

Truth table

Logic circuit

Boolean expression can be derived as minterm or maxterm Boolean expression from truth table and viceversa Logic circuit can be drawn from Boolean expression and vice versa
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From Boolean expression to Logic Circuits

If a logic function is defined by a Boolean expression, its circuit diagram can be implemented directly from the expression In general, there are three type of Boolean expression i. Sum-of-products (SOP) expression ii. Product-of-sums (POS) expression iii. Miscellaneous (a mixture of basic logic functions)

Drawing Logic Circuit from Boolean expression

Y A( B C ) A BC
A B C

AND-OR Networks

These networks are directly drawn from sum-of-products (SOP) expressions Consider the example below:
A B C

AB C

Given Y AB C ABC A C

ABC
AC

Variables are inverted Variables are ANDed together to form product terms Product terms are ORed together
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OR-AND Networks
They are drawn directly from POS expressions Consider the following example
A B C

Given Y ( A B C ) ( A B C ) ( A C )

A B C

A B C
A C

Variables are inverted Variables are ORed together to form sum terms Sum terms are ANDed together
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Other Types of Networks

A

Consist of a mixture of various logic gates, such as NOT, AND, OR, NAND, NOR, XOR, XNOR Example: Y A( B C BC ) C ( A B AB )

Continue ...
Consider another example:

Y ( A B C )( B C D) A B( AC A C )
A B C D

Describing Logic Circuit Algebraically

Similarly, if a logic circuit is given, we can derive its Boolean expression by observing and combining the outputs of each logic gates Consider the AND-OR network below:
A B C

ABC

ABC
Y ABC A B C AB C

AB C

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Continue ...
Consider the following OR-AND network:
A B C
A B

AB
B C

Y ( A B )( A B)( B C )

Consider the following logic circuit:

A B C

AC

BC A C
BC

Y BC( A C ) A
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Consider yet another circuit:

B C D

BD

BD B C
BC

BD B C A C
A C

Y BD B C A C A D
AD

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From Truth Table to Logic Circuit

We can construct the logic circuit from its truth table This can be done by first obtaining the minterm/maxterm Boolean expression from truth table Consider the following example:
A B C Y 0 0 0 0 0 0 1 1 ABC 0 1 0 0 0 1 1 0 1 0 0 1 AB C 1 0 1 0 1 1 0 1 ABC 1 1 1 0
Y A B C AB C ABC

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Continue ...
Consider obtaining the maxterm Boolean expression from the truth table below:
A B C Y 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 A BC 1 0 1 1 1 1 0 1 1 1 1 0 A B C
Y ( A B C )( A B C )

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Evaluating Logic Circuit Output

We can determine the output of a particular logic circuit if its Boolean expression is known This can be done by first obtaining the Boolean expression of the logic circuit and convert it to SOP form
A B C

A B C Y 0 0 0 1 0 0 1 0
A B
BC ( A B )

BC

0 1 0 0 1 1
Y

0 0 0 0 0 1

ABC

1 0 0 1 0 1 1 1 0 1 1 1

Y BC ( A B ) A B C ABC A B C
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Continue ...
Consider obtaining the truth table for the logic circuit below:
A B C

AB
AB BC

BC

Y
AC

A B C Y 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

Y AB BC A C AB BC A C ( A B )(B C ) A C AB AC B C A C
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Continue ...
Consider another logic circuit as shown below:
A B C

A B
A B C

AC

Y
A B C

A B C Y 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

Y A B C A B C ( A B C) ( A B C ) ( A B C )( A B C )

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Continue ...
Consider yet another logic circuit as shown below:
A B C D
A B C D Y 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1

BD

CD
C D AD

AD

B C D AD

Y B D B C D AD B D B C D AD B D B(C D AD) B D BC D ABD

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Universality of NAND & NOR Gates

All Boolean expressions consists of various combinations of OR, AND and NOT Both NAND and NOR gates can be used to perform OR, AND and NOT Thus, it is possible to implement any logic circuit by using only NAND or NOR gates
A
X AA A (a)

A Inverter

Inverter

XAA A (a)

A B

AND

A B A

AB

X AB

(b)
1

A B

OR

A B A

A B

X A B

(b)
1

A
3

A
3

A B

OR

B
(c)

A B

X AB A B

AND

B
(c)

X A B AB

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Implementing AND-OR network with NAND gates only

AND-OR network can be directly implemented using only NAND gates The procedures to convert AND-OR network to pure NAND gates implementation is based on DeMorgans Theorem Consider implementing the AND-OR network below by using NAND gates only
A B C

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Continue ...
A B C
P

Y
P Q R PQR

Implement inverter using NAND gates Place a bubble at the output of each AND gates Place a bubble at the input of the OR gate If an input to OR gate is directly connected to input line, place an inverter between them Redraw the logic circuit by using NAND gates only
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Continue ... Another solution ..

A B C

B C

Y AB AC B

P
Y

AB AC B AB AC Y B
P Q R PQR

Derive the Y output Use De-Morgan to convert SOP to a form of all product Redraw the logic circuit by using NAND gates only based on the derived equation

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Implementing OR-AND network with NOR gates only

Similarly, OR-AND networks can be implemented by using NOR gates only Consider implementing the OR-AND network below by using NOR gates only
A B C

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Continue ...
A B C
P

A B

Y
P Q R P Q R

Implement inverter using NOR gates Place a bubble at the output of each OR gates Place a bubble at the input of the AND gate If an input to AND gate is directly connected to input line, place an inverter between them Redraw the logic circuit by using Nor gates only
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Continue ... Another solution ..

A B C

A B

A B

Y ( A B) ( B C ) C ( A B) ( B C ) C
P

(A B ) (B C) C
Y
Q

Y
P Q R P Q R

Derive the Y output Use De-Morgan to convert POS to a form of all sum Redraw the logic circuit by using NOR gates only based on the derived equation

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Continue ...
The preceding 2 methods can only be applied to ANDOR networks and OR-AND networks, respectively It is advisable to construct logic circuit using NAND or NOR gates only by properly manipulating the Boolean expression of the original logic circuit and application of DeMorgans theorems Consider implement the following logic circuit using NAND gates only:
A B C

A B C

Y AB C AB C AB C

AB Y AB C

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Continue ...
Consider implement the following logic circuit by using NOR gates only:
A B C

Y A B( B C )
AB

A B( B C )
Y

AB B C A B B C

BC

A B

BC

Y B C A B

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Continue ...
Example: i. Implement the following Boolean expression by using NAND gates only:

Y A B BC
Solution:

Y A B BC AB BC AB BC AB BC

AB
BC

Y AB BC

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ii. Implement the following logic function by using NOR gates only:

Y AB BCD
Solution:

Y AB BCD A B BCD A B B C D

AB

AB Y

B C D

A B B C D

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Input and Output Waveforms

We can plot the output waveform of a logic circuit with respect to its inputs by referring to the truth table The procedures to derive the output waveform are: i. Obtain the Boolean expression for the logic circuit ii. Convert the Boolean expression to SOP form iii. Based on the SOP expression, construct the truth table iv. Referring to the truth table, draw the output waveform corresponds to each input condition

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Continue ...
Example: Determine the output waveform if the inputs are varying according to the timing diagram below:
A B C

A 0 1 0 1 1 1 1 0 a b c d e f g h B 1 1 0 0 1 1 0 0

a b c d e f g h C 0 0 1 0 0 1 0 0

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Solution:
A B C
AB
X AB C

X AB C Y C ( A B) AC BC Z AB C
Z AB C

A B
Y C ( A B)

AB

AB C ABC

A B C X 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

Y 0 0 0 1 0 1 0 1

Z 0 0 0 0 0 0 1 0

A 0 1 0 1 1 1 1 0 a b c d e f g h B 1 1 0 0 1 1 0 0 a b c d e f g h C 0 0 1 0 0 1 0 0

X 0 1 1 a b c Y 0 0 0 a b c Z 0 1 0

0 1 1 0 0 d e f g h 0 0 1 0 0 d e f g h 0 1 0 0 0
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Continue ...

Example: Determine the output waveform if the inputs are varying according to the timing diagram below:
A B C D

A 0 a B 1 a C 1 a D 0

0 b 1 b 0 b 0

1 c 1 c 0 c 1

1 d 0 d 1 d 0

0 e 0 e 0 e 1

0 f 1 f 1 f 1

1 g 0 g 0 g 1

1 h 0 h 0 h 0

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Continue ...
A B C D
BD
B D( A C )

AC

B D( A C) AB C D
AB
CD
AB C D

AC D

B ( A C D )( A C D)

( A C D )( A C D)
AC D

Y B D( A C) AB C D B ( A C D )( A C D)
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Continue ...

Y B D( A C ) AB C D B ( A C D )( A C D) B D( AC A C ) AB C D B A C D A C D

AB C D A B CD ( A B)(CD C D) B ( A C D A C D ) AB C D A B CD A CD A C D BCD BC D A B C D A B C D
A B C D Y 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0

A 0 0 1 1 0 0 1 1 a b c d e f g h B 1 1 1 0 0 1 0 0 a b c d e f g h C 1 0 0 1 0 1 0 0 a b c d e f g h D 0 0 1 0 1 1 1 0 Y
1 0 1 0 1 0 1 0
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Electronic Gates

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Faults
Internal shorted inputs or outputs to ground or supply open circuited short between pins

External open signal lines shorted signal lines faulty power supply output loading

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Propagation Delay

Various physical phenomena, such as resistance and capacitance, substantially reduce the speed at which signal can travel in physical circuit If there is a change at the inputs, the output of a logic gate will not change instantaneously. All the delays occur in a logic gate can be grouped into a single average or nominal value, known as the propagation delay Propagation delay is denoted as tpd

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Consider the NAND gate below:
A B X

1 0

A 0 0 1 1

B 0 1 0 1

(A.B)' 1 1 1 0

1 0

1 0

For ideal case, there is no propagation delay and the output responds instantly to the changes of inputs

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If there is a propagation delay, the waveforms will become:
A
1 0

1 0

1 0

tpd

tpd

tpd

The changes in output with respond to the change of input is delayed, by tpd The output waveforms for both cases are the same, but shifted to the right by tpd

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The propagation delay of various gates will introduce glitches in the output waveform Consider the following example:
A Y

1 0

1 0

A
Y

1 0 1 0

A
Y t1 glitch t1

1 0 1 0

(a) Ideal case

t2 (b) w ith propagation delay

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END

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