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Aravind Gurumurthy M.S Thesis Defense Presentation Committee Chair: Dr. Carla Purdy
Goals
Thesis outline
MOSFET transistor MOSFET modeling Different generations of MOS models Experimental setup and models used Results Conclusions and future work
MOSFET transistor
In NMOS transistor as shown, current carried from source to drain by electrons through the n-type channel
MOSFET parameters
Modes of operation
Resistive region:
Saturation region:
MOSFET history
MOSFET modeling dates back 35 years Initially based in V-I and V-C characteristics Modeling has become more complex Current models include effects from short channel and long field strengths
MOSFET history
Source : http://legwww.epfl.ch/ekv/mos-ak/stuttgart/Pregaldiny-mos-ak-STR04.pdf
MOS modeling
Modeling can be defined as The method of finding the parameter values for fixed simulator model equations
MOS modeling -Writing a set of equations that link voltages and currents
Behavior of the device can be simulated and predicted Basic MOS model components 1. 2. Equations describing Ids (Vds) and Ids (Vgs) Parameters that link the technology being used for fabrication
Good I-V characteristic accuracy Meet charge conservation requirement Correct values of small-signal quantities Good prediction for white and 1/f noise Ability to provide results even when device operation is quasi static
Benchmark tests
Benchmark tests used to examine the accuracy For simple circuits unveils the problem areas for a given model
Generation 1
Generation 2
BSIM 1 (LEVEL 13) MODIFIED BSIM (LEVEL 28) BSIM 2 (LEVEL 39)
Generation 3
BSIM 3 (LEVEL 47) **** MOS 9 (LEVEL 50) BSIM 4 (LEVEL 54) EKV (LEVEL 55) **** BSIM3-SOI (LEVEL 59) MOS 11(LEVEL 63) ****
Generation I
Source: Kriplani, N., Transistor modeling using Advanced Circuit Simulator Technology
MOS 1 model
Model equations simple Implements the Shichman-Hodges model Based on gradual channel approximation and square law for saturated drain current
Advantages
Can be used for preliminary circuit simulations Appropriate for long channel and uniform-doping devices
Generation II
Process of modifying the model parameters for different values of drawn channel length and width
HSPICE binning uses multiple model statements modeling a range of different lengths and widths
Model derived from research of General Electric and Intersil Enhanced version of Ids equation from LEVEL 2 model Varies from LEVEL 2 model in the area of
Substrate doping Threshold voltage Effective mobility Channel length modulation Sub-threshold current
MOS 11 model
Symmetrical, surface potential based model Provides accurate physical description of transition from weak to strong inversion
EKV model
Physics based MOSFET model Has less than twenty intrinsic model parameters Specifically geared towards analog circuit simulation Useful for statistical modeling tasks Models available for all major circuit simulators
Overview of experiments
Goal is to show quantitative results proving that by choosing the correct model the results are improved
Hardware description language Verilog-AMS used to compare the results against the results obtained in SPICE
HSPICE
Analog simulator Capable of performing transient, steady state and frequency domain analysis
Title line
Element declaration
Control commands .END
HSPICE (Contd.)
Avanwaves is a point and click interface with bult-in math functions for users
By definition HDL is a programming language for developing executable simulation models of hardware systems
HDLs describe circuits operation and design and also have tests to verify the circuits functionality by simulation
HDLs can be used to design dedicated IC even before the actual circuit is built
The HDL that was used for simulations in this thesis was Verilog-AMS
Verilog-AMS
Supports both analog and digital component description Description in analog components is done by Verilog-A and digital components by Verilog-HDL
Verilog-AMS (Contd.)
Unique feature of this language is the possibility of interconnecting instances of Verilog HDL, Verilog-A and Verilog-AMS with their netlists in a single module
Description of experiments
In this thesis, simulations performed initially for CMOS inverter using a specific MOS model
Then the same MOS model was used in a op-amp circuit to compare the performance when different MOS models are used
Structural level of MOS is used for all simulations Three MOS models were studied MOS 1, MOS 11 and EKVMOS
CMOS inverter
Four terminals gate, drain, source and bulk Specific components were instantiated in Verilog-AMS like the type of transistor, transistor length, width and terminals of each transistor
For spice simulation, a basic inverter was constructed using 0.8 technology and used level 49 BSIM v3 model
The output was observed for all these simulations by varying the W/L ratio of both PMOS and NMOS transistors
Results
Constant supply voltage with varying transistor dimensions Constant W/L ratio (2) with varying supply voltage
Simulations
CMOS Inverter transfer characteristics Structural Model 6 5
Output Voltage (V)
4 3 2 1 0 -1 0 1 2 3
Input Voltage (V) SPICE MOS 1
4 3 2 1 0
-1
3
Input Voltage (V)
SPICE
Verilog-AMS(MOS11)
4 3 2 1 0 -1 0 1 2 3
Input Voltage (V) SPICE EKVMOS
Simulations--Errors
% Error Vs Input voltage (V) 120 100 80
%Error
%Error
% Error Vs Input voltage (V) 200 100 0 -100 -200 -300 -400 -500 0 1 2 3 4 5 6
60 40 20 0 -20 0 1 2 3
Input Voltage (V) MOS 1 and SPICE
-600
Fig 4.4 Relative error between the MOS 1 and SPICE model (Inverter)
% Error Vs Input voltage (V) 120 100 80
%Error
Fig 4.5 Relative error between the MOS 11 and SPICE model (Inverter)
60 40 20 0 -20 0 1 2 3
Input Voltage (V) EKVMOS Vs SPICE
Fig 4.6 Relative error between the EKV and SPICE model (Inverter)
Operational amplifier
Two inputs that operate on dual DC power supply and has a high open-loop gain
Source : R. Jacob Baker, Harry W.Li & David E. Boyce, CMOS Circuit Design, Layout and Simulation
Op-amp parameters
Dimensions of the transistor changed only for the differential stage not the output stage
Simulations performed with 5V dc supply and ramp input given to MOS models had a sweep from -2.5V to + 2.5V
Source: Simon Foo, Lisa Anderson & Yoshiyasu Takefuji Analog Components for the VLSI of Neural Networks IEEE, 1990
The value of output follows the function f(x)=0 for x <= 1 1 for x > 1
Simulations
Unit Step Function Structural Model
5 4 2 1 -3 -2 -1 0 -1 0 -2 -3 -4 -5 Input Voltage (V) 1 2 3
4 2 0 -3 -2 -1 -2 -4 -6
Input Voltage (V) SPICE Verilog-AMS(MOS 11)
Verilog-AMS(MOS1)
SPICE
-3
-2
-1
% Error
% Error Vs Input Voltage
250 200
Error(%)
80 60 40 20 0 -3 -2 -1 0
Input Voltage (V)
Error(%)
EKVMOS Vs SPICE
Source: Simon Foo, Lisa Anderson & Yoshiyasu Takefuji Analog Components for the VLSI of Neural Networks IEEE, 1990
Simulations
Linear Function (Fixed Threshold) Structural Model 5 4 3 2 1 0 -1 0 -2 -3 -4 -5
Input Voltage (V) Verilog-AMS(MOS 1) SPICE
-3
-2
-1
-3
-2
-1
-3
-2
-1
% Error
% Error Vs Input Voltage(V)
20 10
Error(%)
-3
-2
%Error
d2-f2
-3
-2
-1
100 50 0 -3 -2 -1 0
Input Voltage (V)
Conclusion
Output voltages for different MOS models for both inverter and
advanced
MOS
models
have
better
Conclusion (Contd.)
MOS 11 and EKVMOS models available for use in this thesis dont represent the complete models
Verilog-AMS models currently available not mature enough to get results as expected
Future work
To improve accuracy, improve the current models Open source library of models can be developed
THANK YOU
Questions??
Supplementary Slides
Disadvantages
Not accurate for models with submicron geometries Has convergence problems Slower
Disadvantages
Doesnt have narrow width effects No short-channel effects Model parameter TPG defaults to zero for aluminum gate and for other levels, it defaults to one
Enhancement Depletion
If the mode parameter ZENH value is 1, then its the enhancement model else its the depletion model
Model binning can be accomplished Model parameter is set empirically Geared towards analog design
Enhanced version of BSIM3 Accounts for the physical effects when the 100nm regime is reached
Accurate model of intrinsic input impedance for analog, digital and RF applications
Physics based model specifically geared towards analog simulation developed by Philips
Very good description of electrical characteristics for all regions of transistor operation
Even using one parameter set, behavior of the model over a wide range of lengths and widths
Appropriate not only for circuit design, process technology but also in CAD tool development