RRASE COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BATCH NO: 08

NIOS 2 PROCESSOR BASED CUSTOMIZED SOFT MCU FOR A WEBSERVER IMPLEMENTATION ON FPGA
Submitted by : M. Ramesh (44509106017) M. Selvasekar (44509106023) K.Kannapan (44509106308) R. Prasath (44509106706)

Guided by: Mr.T.V.Karthick

OBJECTIVE

The main aim of this project is to control the FPGA microprocessor kit accessing anywhere on the world through the web using the NIOS 2 software platform. The microprocessor kit get interfaced to the computer connecting to the web through the EWS device and can be programmed as per our wish and applied it practically by connecting peripheral devices.

PROJECT BLOCK DIAGRAM

Relay Drivers Internet TCP/IP network

Relays

Devices And Appliances

EWS

FPGA (NIOS II)

CYCLONE II FAMILY

Altera Cyclone II FPGAs extend the low-cost FPGA

density range to 68,416 logic elements (LEs). Cyclone II devices can support complex digital systems on a single chip at a cost that are equivalent to ASICs. Cyclone II devices support the Nios II embedded processor which allows you to implement custom-fit embedded processing solutions. They are available in different packages ranging from 144pins to 672 pins. They are available in three different speed grades for different processing speed requirements.

FPGA BLOCK DIAGRAM

Power Supply Input Buffer

JTAG Interface

Output Buffer

Active Serial Programming Interface

General Purpose I/O FPGA RS232 Interface USB Interface

Configuration Memory Oscillators Reset Switch

Indicator LEDs

EP2C8T144C8

EP2C8T144C8 is the FPGA used in the project it has:

8,256 Logic Elements Comes in a 144pin TSOP package The core working voltage is 1.2V The Maximum I/O voltage is up to 3.3V Out of the 144 pins 89 Pins can be used as general

purpose I/Os. It is available in three different speed grades, the one used in the project is speed grade 8.

NIOS 2

A Nios II processor system is equivalent to a

microcontroller or computer on a chip that includes:

A processor core Combination of peripherals On chip memory Off chip memory A dedicated instruction set

All of these can be implemented on a single Altera FPGA. It is possible to implement many NIOS processors on a

single FPGA also. Three different configurations of NIOS II processors are available namely
NIOS II F (Fast) NIOS II S (Standard) NIOS II E (Economy)

NIOS 2 The Nios II processor is a general-purpose RISC processor core, providing: Full 32-bit instruction set, data path, and address space 32 general-purpose registers Optional shadow register sets 32 interrupt sources External interrupt controller interface for more interrupt sources Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals Optional memory management unit (MMU) to support operating systems that require MMUs Optional memory protection unit (MPU)