VLSI

What is VLSI?
Very Large Scale Integration SSI Small-Scale Integration (0-102)---1960 MSI Medium-Scale Integration (102-103)---1967 LSI Large-Scale Integration (103-105)---1972 VLSI Very Large-Scale Integration (105-107)---1978 ULSI Ultra Large-Scale Integration (>=107)---1989 GSI _ Giant Scale Integration (>=109)---2000

*Where these are given as no of transistors.

Integration Level Trends

Obligatory historical Moores law plot

 Integrated Circuits/MEMs
Hierarchy of various technology Semiconductor process
Silicon GaAs

Bipolar ECL

Unipolar

Bipolar

Unipolar

NMOS

PMOS

TTL

CMOS

Chips

Integrated circuits consist of:

A small square or rectangular die, < 1mm thick Small die: 1.5 mm x 1.5 mm => 2.25 mm2 Large die: 15 mm x 15 mm => 225 mm2 Larger die sizes mean: More logic, memory Less volume Less yield Dies are made from silicon (substrate) Substrate provides mechanical support and electrical common point

Advancements over the years

Intel 4004 Processor Introduced in 1971 2300 Transistors 108 KHz Clock

Intel P4 Processor Introduced in 2000 40 Million Transistors 1.5GHz Clock

System Design Pyramid

Photolithography and Patterning

Photo-litho-graphy: latin: light-stone-writing
Photolithography: an optical means for transferring patterns onto a substrate. Patterns are first transferred to a photoresist layer. Typically a wafer is about 8-10 inches in diameter. Individual ICs are placed inside it.

Photoresist is a liquid film that is spread out onto a substrate, exposed with a desired pattern, and developed into a selectively placed layer for subsequent processing.
Photolithography is a binary pattern transfer: there is no gray-scale, color, nor depth to the image.

Steps Photo resist Coating (covering) A light sensitive organic polymer (plastic)
Mask/ Reticle formation Exposure to light (UV/X-RAY/E-BEAM)

WHAT IS A PHOTOMASK?

Photomasks are high precision plates containing microscopic images of electronic circuits. Photomasks are made from very flat pieces of quartz or glass with a layer of chrome on one side. Etched in the chrome is a portion of an electronic circuit design. This circuit design on the mask is also called geometry.

The Resist
The first step is to coat the Si/SiO2 wafer with a film of a light sensitive material, called a resist.
Solvent Evaporates

A resist must also be capable of high fidelity recording of the pattern (resolution) and durable enough to survive later process steps

Photolithography
Energy Mask + Aligner Photoresist Wafer Energy
dissolution rate

causes (photo)chemical reactions that modify resist

Mask - blocks energy transmission to some areas of the resist Aligner- aligns mask to previously exposed layers of the overall design Resist - records the masked pattern of energy

Next Generation Lithography

In 1996, five technology options were proposed for the 130 nm gate length technology: X-ray proximity Lithography (XPL)

Extreme Ultraviolet (EUV)

Electron Projection Lithography (EPL) Ion Projection Lithography (IPL)

Direct-write lithography (EBDW).

These options were referred to as the next generation lithography.

MOSFET Design Rules

Lambda based design Rule

Micron Rule

Minimum width and Spacing

Layer Poly Active N select Metal Value 2L 3L 3L 3L

Stick Diagrams
Metal

poly ndiff
pdiff
Can also draw in shades of gray/line style.

 Wiring Tracks A wiring track is the space required for a wire

4 l width, 4 l spacing from neighbor = 8 l pitch

Transistors also consume one wiring track

 Well spacing Wells must surround transistors by 6 l

Implies 12 l between opposite transistor flavors Leaves room for one wire track

Stick Diagrams

Basic Circuit Layout

VDD VDD

X
X X

Stick Diagra m

X Gnd

Gnd

Stick Diagrams

Layout Diagrams
VDD X X X VDD

X Gnd

Gnd

Example: Inverter

MOSFET Arrays and AOI Gates

A B C

x A B C

Parallel Connected MOS Patterning

x x A X B X

X y

Alternate Layout Strategy

x x X A B A X X B X

MOSFET Arrays and AOI Gates

NAND2 Layout Vp Vp

a.b a.b
X Gnd X

Gnd

b
a

NOR2 Layout
Vp Vp X X

ab

a
Gnd

ab
X

b
Gnd

Stick Diagrams

Power

Out

C B
Ground

Cells, Libraries, and Hierarchical Design

Creation of a Cell Library
VDD X X

X X

x
X

X X

X Gnd

VDD X X X X

a
X

xX
X

X X

a.b

a.b
Gnd

VDD X

X
X X

a
X X

x
ab
X X X

ab

b
Gnd

 Cell Placement System Hierarchy (MOSFET-Gates-F/FsRegisters-Networks-Systems) Floorplans and Interconnect Wiring Y= (# of Good Chips/Total No)*100% Y=Yield Y depends on total area=A, and no of defects=D, Y=e
AD

*100%

Interconnects
Place and Route Algorithm. Wiring Delay td=kl2 l=length of inter connect.
td