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A flip-flop or latch is a circuit that has two stable states and can be used to store state information.

A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic.

The circuit has two stable states Such a circuit is called a flip-flop or latches Latches and flip-flop store information Latches change output on changes to input Flip-op change output only when the clock changes

Flip-flops can be either simple (transparent) or clocked (synchronous or edge-triggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flop.

Flip-flop types Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output,Q next, in terms of the input signal(s) and/or the current output, Q

Simple set-reset latches SR NOR latch

An SR latch, constructed from a pair of cross-coupled NOR gates (an animated picture). Red and black mean logical '1' and '0', respectively. When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

SR latch operation Characteristic table S R Qnext Action 00Q hold state 010 reset 101 set 11X not allowed

Excitation table Q Qnext S R 000X 0110 1001 11X0

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency digital circuits. Although this condition is usually avoided, it can be useful in some applications. To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-restricted combinations. That can be: Q = 1 (1,0) referred to as an S-latch Q = 0 (0,1) referred to as an R-latch Keep state (0,0) referred to as an E-latch Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch. Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.

XOR Gate
An XOR gate accepts two input signals

If both are the same, the output is 0; otherwise, the output is 1

Figure 4.4 Various representations of an XOR gate

XOR Gate
Note the difference between the XOR gate and the OR gate; they differ only in one input situation When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0

XOR is called the exclusive OR


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Adders
At the digital logic level, addition is performed in binary Addition operations are carried out by special circuits called, appropriately, adders

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Adders
The result of adding two binary digits could produce a carry value Recall that 1 + 1 = 10 in base two Half adder A circuit that computes the sum of two bits and produces the correct carry bit

Truth table

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Adders
Circuit diagram representing a half adder Boolean expressions

sum = A B carry = AB

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Adders
Full adder A circuit that takes the carry-in value into account

Figure 4.10 A full adder


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Multiplexers
Multiplexer A circuit that uses a few input control signals to determine which of several output data lines is routed to its output

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Multiplexers
The control lines S0, S1, and S2 determine which of eight other input lines (D0 D7) are routed to the output (F)

Figure 4.11 A block diagram of a multiplexer with three select control lines

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