Application of Self Organizing Maps for Investigating Network Latency on Broadcast-based Distributed Shared Memory Multiprocessor

INTRODUCTION
Distributed shared memory(DSM) multiprocessor, which represent a successful hybrid of two parallel computer classes :1. Shared memory multiprocessor 2. Distributed computer systems.

DSM multiprocessor systems are an attractive and viable platform for both Parallel and Mainstream computing. Due to its advantages in terms of 1. Scalability 2. Programmability 3. Cost effectiveness

Aim of DSM system

To combine of PROGRAMMING of shared memory multiprocessors with the SCALABILITY of distributed computer systems.

DSM system

Remote Memory Latency

To achieve high performance in DSM multiprocessor Remote Memory Access time must be minimized RML is caused by accessing a memory location in a processor other than the one originating the request Network latency is major component of remote memory latency Cause most of the time is consumed in communication over the interconnection network

Developing methods to minimize the network latency in broadcast-based optical DSM multiprocessors requires the knowledge of the effect of DSM parameters on the network latency

Self-Organizing Maps

Overview

Self organizing map (SOM) is a data visualization technique invented by kohonen

SOM is a way to represent higher dimensional data in an usually 2-D or 3-D manner, such that similar data is grouped together.
It runs unsupervised and performs the grouping on its own. SOM is accepted as Analysis tool.

SOM Structure (kohonen)

Every node is connected to the input the same way, and no nodes are connected to each other. In a SOM that judges RGB color values and tries to group similar colors together, each square pixel in the display is a node in the SOM. Notice in the converged SOM above that dark blue is near light blue and dark green is near light green.

We use SOM to investigate the realtionship between the network latency and several DSM parameters on the Simultaneous Optical Multiprocessor Exchange Bus(SOME-Bus) SOME-Bus is high bandwidth, optical and broadcast-based interconnection network supporting DSM.

An event based discrete simulator

Is developed for simulating a SOME-Bus system Which containing 64 nodes, Each of which has Processor, a Directory controller, A cache controller, and an output channel.

Node model of DSM-based SOME-bus system

State diagram of acb_fifo in OPNET modeler

init
arrival
Server busy & insert ok Queue empty

start
arrival default arrival default Svc completion

comp l

default

idle

Dataset details

1.

Two thousand data points have been collected in order to create a dataset for study. Dataset includes 6 parameters
Miss rate to a modified block (Pm) Fraction of write misses (Pw) Probability of having an upgrade ownership request message (Puor) Probability of having a cache full (Pcf) Ratio of the mean thread run time to mean message transfer time (T/R) Network latency

2.
3.

4. 5.

6.

In observed simulation Pw ranges from 0.15 to 0.7 Pm takes values varying between 0.2 and 0.6 The ration varies between 0.05 and 1

Let m =miss rate F= number of instruction per second performed by the processor at each node, S= mean msg size in bytes and C= channel bandwidth(bytes/s) Ratio of the mean thread run time to the mean message transfer time T/R=mSF/C

CONCLUSION
This paper presents a new application domain for the use of SOM. In this paper SOM have been used to investigate the ralation between network latency and important DSM parameters The result shows that network latency has highest correlation with T/R while Pcf has the least effect on the values of network latency

Puor requires high Pw values to demonstrate strength on network latency values. Low values of Pw and Pm will yield low network latencies Low values of Pw together with high values of Pm have a detractive effect on network latency