Jonathan Bromley Doulos

DVClub Bristol 22-April-2009
The Verification Methodology Landscape
Jonathan Bromley, Doulos

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Copyright 2008 by Doulos. All rights reserved.
The Verification Methodology Landscape
CONTENTS The M-word Languages, methodologies, tools and standards The big players: OVM, VMM, eRM
Interoperability and convergence

Conclusions?
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Verification Environment
Coverage collector
Scoreboard / Checker
Transaction recording
Test controller Monitor
TLM
Stimulus generator Driver DUT
Transactions
Constrained Random Verification

Checker Constrained random stimulus Did we see a bug?
11001001 01001010 00001001 01110110 01100110 01001001 01001110
Design Under Test
000010 010011 000010 100100 001000 110010 000011 Functional Coverage

Are we done?
4
Constraints
Header Payload Checksum
Increase coverage
The Verification Space

Verification Formal Verification Acceleration + Emulation Property Checking Equivalence Checking
Simulation
Dynamic Formal
Simulation Simulation Simulation Formal Simulation Formal
Transaction Level Modelling
Constrained Random Intelligent Testbench
Assertions
Coverage
What Our Customers Want
Ease of deployment

Customizable environment
but it must do something useful straight out of the box
Simple, uniform interface to any verification IP block Gentle learning curve for the whole team
Power
Complex testcases co-ordinated across the whole environment Randomization Sophisticated coverage analysis
Interoperability
Every customer we meet has legacy verification IP
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Methodology (or just a toolkit?)
Tame the language monster

e, SystemVerilog, C++ are big and complicated Many ways to solve a problem Wheel reinvention is a hazard
Toolkit
OOP encourages encapsulation of standard functionality in base classes Ideal for component hierarchy, reporting, block-to-block communication, DUT connectivity
Methodology

Published methodology encourages interoperability and re-use Promote best practice
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Mature Language Standards

List unchanged for 4 years...
Crude Caricature
FPGA, RTL, Europe, Mil-Aero
IEEE 1076 VHDL

IEEE 1850 PSL
IEEE 1364 Verilog
ASIC, RTL, USA/RoW Hardware verification
IEEE 1800 SystemVerilog
IEEE 1647 e
Hardware verification
ISO/IEC 14882 C++ IEEE 1666 SystemC
Modelling, verification Virtual hardware prototypes for S/W dev
Tcl/Tk, Perl
Scripting
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New Standards Activity
Verilog and SystemVerilog unified
LRM this year, currently in ballot feedback Major enhancements to assertions
Verification methodology
OVM 2.0, OVM-SC VMM open-source eRM3 - e / SV interoperability (Cadence) OVM / VMM interoperability (Accellera)
SystemC TLM-2.0
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The Big Methodology Players
www.ovmworld.org
www.vmmcentral.org
eRM
www.cadence.com
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Static View of Testbench

Environment Configuration checker
eRM
Sequencer active agent Driver BFM Monitor BFM
Sequencer passive agent Driver BFM Monitor BFM
simple ports (e) virtual interfaces (SV)
DUT
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Static View of Testbench (VMM)

... test_env env = new; env.run(); ...
Constraints; directed tests
Generator
High level transactions Atomic transactions
Self Check
Transactor
Monitor
Functional Coverage
Checker
Driver
Properties
Checker
Monitor
DUT
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OVM Key Features

Constrained random, coverage-driven verification Separation of tests from verification environment Configuration of verification environment
through a table (canonical structure and guidelines)
Verification IP reuse
TLM communication Automation

(where missing from SystemVerilog language)
Hierarchical sequential stimulus (sequences)
Standardized messaging
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eRM Key Features

Constrained random, coverage-driven verification Separation of tests from verification environment Configuration of verification environment
through AOP extension and pre-run constraints (rigorously standardized rules)
Communication via ports Automation

(using e language's macro features)
Hierarchical sequential stimulus (sequences)
Standardized messaging
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VMM Key Features

Constrained random, coverage-driven verification Configuration of verification environment
through configuration objects passed to verification components (conventions)
Communication via channels, callbacks, notifications Automation

(scripts and macros)
Hierarchical sequential stimulus (scenarios) Standardized messaging
Strongly influenced by RVM (Synopsys Vera)

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Structure of an OVM Component

class my_driver extends ovm_driver #(my_transaction);
Base class TLM port (inherited) Connection to DUT Constructor
// ovm_seq_item_pull_port #(...) seq_item_port;

my_dut_if_wrapper m_dut_if; function new(string name, ovm_component parent); super.new(name, parent); endfunction: new function void build; super.build(); endfunction: build
Build phase callback
virtual task run; forever begin ... end endtask: run endclass: my_driver
Run phase callback
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Phase Methods (OVM)

build connect end_of_elaboration start_of_simulation run extract check report
Call factory Make TLM connections After connections hardened
Get ready to run

Task (executed concurrently)
Post-processing
Similar phase arrangements in VMM, eRM

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Reconfigurable Environment (OVM)

By type or instance path
set_inst_override_*
Test Test
Customize environments
set_config_*
Reusable verification environment
Customize types
Scoreboard
Virtual sequencer
set_type_override_*
Config
Sequencer
Monitor
Existing verification component
Existing verification component
Monitor
Driver
DUT
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Layered Sequential Stimulus

Tests enumerate possible top-level sequences
Virtual or layered sequences
seq1
seq2
seq2
Constrained random sequence of transactions

Randomized transactions are not enough
tx1
tx2
tx3
Drive transactions into DUT
tx1
Driver
DUT
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Virtual Sequences
Component hierarchy ovm_env Stimulus hierarchy (co-ordinated interfaces)
ovm_sequencer
ovm_sequence
ovm_agent
ovm_agent
ovm_sequencer
ovm_sequencer
ovm_sequence
ovm_sequence_item
ovm_driver
ovm_driver
dut_if DUT
dut_if
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Scenario Generator (VMM)

Verification environment Scenario generator scenario_set [0] atomic burst items
select_scenario
select
[1] burst
[2] RMW
copies of items
generator's output channel
Downstream transactor
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Now and Next
VMM: rapidly growing collection of "applications"
register abstraction layer, hierarchy, ...
OVM/VMM interoperability toolkits/standards
OVM/eRM mixed-language tools
OVM-SC
Increasing availability of verification IP

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Conclusion

Interesting times
standards don't always keep up with user needs
Challenges for users choosing a new approach:
tools? methodology? decisions are not yet completely decoupled
Training is important:
VMM, OVM, eRM are not difficult ...

... but jump-starting your efforts pays dividends
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Jonathan Bromley Doulos

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DVClub Bristol 22-April-2009

The Verification Methodology Landscape

Jonathan Bromley, Doulos

The Verification Methodology Landscape

Interoperability and convergence

Test controller Monitor

Constrained Random Verification

11001001 01001010 00001001 01110110 01100110 01001001 01001110

Design Under Test

000010 010011 000010 100100 001000 110010 000011 Functional Coverage

The Verification Space

Transaction Level Modelling

Constrained Random Intelligent Testbench

Copyright 2008 by Doulos. All rights reserved.

What Our Customers Want

but it must do something useful straight out of the box

Methodology (or just a toolkit?)

Tame the language monster

Mature Language Standards

IEEE 1076 VHDL

IEEE 1364 Verilog

ASIC, RTL, USA/RoW Hardware verification

IEEE 1800 SystemVerilog

ISO/IEC 14882 C++ IEEE 1666 SystemC

Modelling, verification Virtual hardware prototypes for S/W dev

New Standards Activity

Verilog and SystemVerilog unified

LRM this year, currently in ballot feedback Major enhancements to assertions

The Big Methodology Players

Static View of Testbench

Sequencer active agent Driver BFM Monitor BFM

Sequencer passive agent Driver BFM Monitor BFM

simple ports (e) virtual interfaces (SV)

Static View of Testbench (VMM)

Constraints; directed tests

OVM Key Features

through a table (canonical structure and guidelines)

TLM communication Automation

Hierarchical sequential stimulus (sequences)

eRM Key Features

through AOP extension and pre-run constraints (rigorously standardized rules)

Communication via ports Automation

Hierarchical sequential stimulus (sequences)

VMM Key Features

through configuration objects passed to verification components (conventions)

Communication via channels, callbacks, notifications Automation

Hierarchical sequential stimulus (scenarios) Standardized messaging

Strongly influenced by RVM (Synopsys Vera)

Structure of an OVM Component

Base class TLM port (inherited) Connection to DUT Constructor

// ovm_seq_item_pull_port #(...) seq_item_port;

Build phase callback

Run phase callback

Phase Methods (OVM)

Call factory Make TLM connections After connections hardened

Get ready to run

Similar phase arrangements in VMM, eRM

Reconfigurable Environment (OVM)

Reusable verification environment

Existing verification component

Existing verification component

Layered Sequential Stimulus

Virtual or layered sequences

Constrained random sequence of transactions