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Masks and Layouts

Introduction
Weve learned all of the standard DRs
EE271, taping out 0.8 to 0.25mm chips

There are also a number of newer DRs


For more advanced processes, fab steps They may affect you in future tapeouts

A brief intro to some of these rules


Not sure what processes use these...

Outline
New metal density rules

Antenna rules and proper application


Phase-shift region coloring Optical proximity correction Odds and ends

Metal Density
Old rule: minimum metal density
For Al, metals were etched away
resist
This etching step takes a lot longer (microloading)

metal
ILD
High density Low density

Solution: Add dummy metal structures here to maintain minimum metal density

Metal Density
New rule: max/min metal density
For Cu, metals are poured (damascene) Review of dual-damascene

Ta barrier layer to prevent Cu from diffusing into Si

M2

SiN layer for etch stop

M1

An amateurs view of dual damascene (via-first variation)

Metal Density
Min rule: Ta barrier is hard to remove Max rule: Cu metal is much softer than Ta Selectivity of Cu is 20x higher than for Ta

Barrier tough to remove

Softness of Cu results in dishing

Low density: Mandate min. metal density

High density: Mandate max. density and width

Metal Density
Min density:
Around 30%/layer, in stepped windows Windows are around 1mmx1mm square, steps of ~100mm Dummification metal structures required to add metal

Max density
Around 70%/layer, again in stepped windows Usually, max width + min spacing -> 90% density Insert slots in lines or turn wide wires into parallel lines

Rules checked in Dracula (not Magic)

Antenna Rules
Reactive ion etch charges up metal lines
Charge can accumulate and zap a gate oxide If a gate sees a long metal before a diffusion does

m4 m3 m2 m1

100l

2000l

gate

diff

gate
Dangerous: lots of m3; will probably accumulate lots of charge and then blow oxide

diff

Safe: m3 is too short to accumulate very much charge; wont kill gate

Antenna Rules
Two solutions: bridging and node diodes
Bridging attaches a higher layer intermediary Diode is a piece of diffusion to leak away charge

m4 m3 m2 m1 gate

2000l

diff psub Bridging keeps gate away from long metals until they drain through the diffusion

gate

ndiff

Node diodes are inactive during chip operation (reverse-biased p/n); let charge leak away harmlessly

Antenna Rules
Bridge or add node diodes if area ratio > limit
Most rulesets today use Sum(metal_area_not_tied_to_diff)/gate_area Examples from previous slides

Be careful to account for etch rate!


Etching rates vary depending on geometries May expose antennas of smaller or larger size Note: this applies to Al, not Cu damascene

Antenna Rules
In areas of lower metal density (microloading)
Slower etch can imply longer-lasting islands

Node x

Large island of metal lasts for a short time, but can be enough to gather a fatal charge, especially if node X were already close to the ratio limit

Antenna Rules
In regions of lots of narrowly space wires
Can get a slower etch effect from e- shading Especially if resist aspect ratio is high Etching particles dont enter trench as easily Differential in etch rates, creating islands of metal
a b c d

Node c, e.g., has an etch-antenna that includes a, b, and d

Antenna Rules
Antenna rules work incrementally
Disconnect all above M1; check non-diff nodes Add M2; check non-diffusion-protected nodes; etc. Stefanos has such a flow for Magic (ext2ant)

Ideally, antenna rules would include etching


Calculate ratios based on neighbors and etchrates
In practice, use a fudge factor on the allowed ratio

Cu relaxes antenna rule (lower ratio)


Still must etch ILD, but no etchrate variability

Phase-Shifting Masks
Lithography uses (partially) coherent light
Wavelength today is 248nm; changes slowly

Kahng et. al., 1999 DAC

Phase-Shifting Masks
PSM enables higher resolution patterning
Exploiting constructive/destructive light

Kahng et. al., 1999 DAC

Phase-Shifting Masks
PSM done typically on poly and contact
Most critical layers for narrow lines; PSM $$$

Around any line, we need to flip phases This is a 2-coloring problem


0o 180o 0o 180o

180o
0o 180o

0o

180o
0o 180o

0o
Phase conflict here will create an unwanted line; need trim mask to kill it

Phase-Shifting Masks
Two principal design rule effects
Orthogonal gates cannot be too close Avoid interdigitating poly These should be checkable directly in Magic

0o 180o 180o
Orthogonal gates need to have increased spacing to allow room for the 0o section to the right of the vertical gate

Trying to duck the poly-poly rule by interdigitating the fingers is bad

Optical Proximity Correction


Also known as serifs and dog-ears
Layout is not WYSIWYG anymore

Patterning through a reticle is tough


Holes in reticle act as low-pass filter Blurred edges Squares in mask are blobby ovals in production We can predistort the image to compensate Analogous to channel equalization

Optical Proximity Correction


Standard fixes include:
Outside corner dog-ears Inside corner cut-outs Long line embellishments

Optical Proximity Correction


Example

Schellenberg et. al., 1999 SPIE

Optical Proximity Correction


This is a back-end flow, done after tape-out
Designers are unaware of OPC for the most part Only real restriction: limit use of 45o routing 45o routes, with OPC, need more spacing to other wires Only important to those of us who use Cadence tools...

OPC does explode the database size Imagine the size of a microprocessor database...

Odds and Ends


Via spacing rules will change
Center-to-center instead of edge-to-edge Reflect the fact that vias are really more circular Most efficient packing is not a rectangular array More like a checkerboard pattern Checkable in Magic (shrink, then edge-edge)

Odds and Ends


EM rules are relaxed with Cu metal
Vias in Cu processes are also Cu (poured) Expect that via EM rules are also relaxed However, vias have some EM problems Void formation at vias Defects in the hole formed during the dielectric etch Void formation along the Cu wire Adhesion of the Cu to the barrier metal above isnt great Voids will travel down the wire and get stuck in the vias

CMOS transistors are fabricated on silicon wafer Wafers diameters (200-300 mm) Lithography process similar to printing press On each step, different materials are deposited,

or patterned or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires to make an n-well for body of pMOS

transistors
A GND Y VDD SiO 2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

Well and Substrate Taps


Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor

connection called Schottky Diode Use heavily doped well and substrate contacts/taps A (or ties)
GND Y VDD

p+

n+

n+ p substrate

p+ n well

p+

n+

substrate tap

well tap

Inverter Mask Set


Top view
Transistors and wires are defined by masks Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

Detailed Mask Views


Six masks
n-well Polysilicon n+ diffusion p+ diffusion
n+ Diffusion Polysilicon n well

Contact

Metal

p+ Diffusion

Contact

In

In reality >40 masks may be needed


Metal

End of session
29 5/24/2013