Assert and Report Statements

Once the VHDL model is made, next step is to test it. VHDL provides some special statements such as assert, report, and severity for testing process.

The assert statement checks to see if a certain condition is true and if not, it causes an error message to be displayed assert boolean-expression report string-expression [severity severity-level;] There are four possible severity levels: Note Warning Error Failure The severity level is optional. Assert and Report statements are very useful for creation of test benches.

Entity DFF is port (D,CLK:in bit; Q,NOTQ:out bit); End DFF; Architecture CHECK_TIME of DFF is constant HOLD_TIME:TIME:= 5ns; constant SETUP_TIME:TIME:= 3ns; Begin process(D,CLK) variable lasteventonD, lasteventonCLK: TIME; Begin ---check for hold time If DEVENT then assert now=0 ns or (now-lastevevntonclk)>= HOLD_TIME Report Hold time too short! Severity FAILURE; lasteventonD:=now; End if;

--Check for setup time

If CLK =1 and CLKEVENT then assert now=0 ns or (now-lasteventonD)>=SETUP_TIME report setup time too short! Severity FAILURE; Lasteventonclk:= now; End if; --behavior of FF If CLK=1 and CLKEVENT then Q<= D; NOTQ<= not D; End if; End process; End CHECK_TIME;

DIGITAL SYSTEM DESIGN

AUTOMATION

RTL Design Flow:

Design Entry
---The first step in the design of a digital system: Describing the design in VHDL in a top-down hierarchical fashion. Register Transfer Level (RTL): High-level VHDL designs usually described at this level.

--VHDL constructs used in RT level design:

Sequential statements for high-level behavioral descriptions. Signal assignments for representing logic blocks, bus assignments, bus and input/output interconnect specifications. Instantiation statements for using lower-level components in an upper level.

Test Bench in VHDL

Simulation and Test of a designed system functionality before Hardware generation. Detection of design errors and incompatibility of components used in the design. By generation of a test data and observation of simulation results. Testbench: A VHDL module Use of high-level constructs of VHDL for: Data Generation Response Monitoring Handshaking with the design Inside the Testbench: Instantiation of the design module. Test bench forms a simulation model together with the design, used by a VHDL simulation engine.

RTL Simulation Flow:

Waveform Output

RTL Synthesis:
Synthesis is the process for automatic design generation from a design description. for ex. We have to specify a target hardware (ASIC, FPGA, CUSTOM IC) --sysnthesis will specifiy the timing and functional specification for compilation process.

-- Compiler converts various parts of the design to in intermediate format(analysis phase), links all parts together, generate the corresponding logic (synthesis phase), place and route components according to the target hardware and generate timing specification.

Place and Route Data Flow:

Timing Analysis:
This phase generate : worst-case delay, clocking speed, delay from one gate to another, Setup time hold time Designer used this information to decide the speed of the circuit.

Post layout timing simulation:

To check the Timing issue, determination of proper clock frequency and race and hazard considerations.

HDL Existing Language

AHPL (A hardware programming language) CDL (Computer design language) CONLAN (CONsensus language) IDL (Interactive design language) ISPS (Instruction set processor specification) TEGAS (Test generation and simulation) TI-HDL (Texas instrument hardware description language) ZEUS

VHDL Requirement
--Some specific requirements of VHDL are as follows: --As per DoD (department of defense requirement for hardware description language) General Features Support for Design Hierarchy Library Support Sequential Statement Generic Design Type Declaration and Usage Use of Subprograms Timing Control Structural Specification

The VHDL Language

A hardware description language with strong emphasis on concurrency. Supports hierarchical description of hardware from system to gate or even switch level. Strong support at all levels for timing specification and violation detection. Provides constructs for generic design specification and configuration.

A VHDL design entity is defined as: An entity declaration Its associated architecture body
Groups subprograms or design entities by use of packages. Configurations for customizing generic descriptions of design entities. Supports libraries and contains constructs for accessing packages, design entities, or configurations from various libraries.

RTL Design with VHDL:

1) Basic structure of VHDL

2)Combinational Circuits 3) Sequential Circuits 4) Writing Test Benches 5) Synthesis issue 6) VHDL essential terminology

1) Basic structure of VHDL:

Simulation in VHDL

Synthesis of a VHDL design

Post synthesis simulation in VHDL

a) Entity and Architecture : A single entity contain multiple architecture. b) Entity-architecture pair: In case of entity-architecture pair we define the term module and that module can be described in a hierarchical manner

c) Entity port: It includes input, output, bidirectional input/output lines. IN : input port OUT: output port INOUT: bidirectional input-output ports BUFFER: for buffered output

TO for ascending range DOWNTO for descending range Vectors are declared by the vector type (BIT_VECTOR)

d) Signals and Variables: e) Logic value System: Standard VHDL define BIT(0 and 1) for basic logic values type. Similarly std_logic standard package define a nine values logic system.

Logic value system

NOTE: TheU logic value is considered as the default value for objects that do not specify an initial value.

f) Resolutions: VHDL allows multiple concurrent assignment to resolved signals.

If av=00001111 bv=00111100 When as and bs =1 then yv= 00XX11XX If av=00001111 bv=00111100 When as =1 and bs=0 then Yv =00001111

Resolved Function

2) Combinational Circuits:
a) XOR example

b) Adder example

c) Multiplexer example

d) Decoder example

 A combinational circuit may be described by the use of Boolean, logical and arithmetic operations. for this description VHDL can use a set of operators as follows:

VHDL can also use sequential statements (process) for combinational networks.

3) Sequential Circuits:
A sequential circuit can be described in VHDL by use of gates, Boolean expressions, or behavioral constructs( process statement) .

We can take any example of sequential circuits as: a) Latches b) Flip flop c) Registers d) Shifters and Counters e) State Machines f) Memories

4) Writing Test benches: A test bench is a model that is used to exercise

and verify the correctness of a model. A test bench has three main purpose: 1) To generate stimulus for simulation(waveforms) 2) To apply this stimulus to the entity under test and collect the output response 3) To compare output response with expected value A typical Test Bench format is: entity test_bench is end; architecture tb_behavior of test_bench is component entity_under_test port (list of port-their types-andmodes); end component; local signal declarations; begin apply-to-entity-under test EUT: entity_under_test port map (port-association); Monitor-values-and-compare-with-expexted-values; end tb_behavior;

There are two main approaches in generating stimulus value:

1) Crete waveform and apply stimulus at certain discrete time intervals. 2) Generate stimulus based on the state of entity, that is, based on the output

response of the entity.

5) VHDL essential Terminologies: this topic provides the linguistic aspects

of VHDL language.
Design Analysis

Library
Work Library STD Library

IEEE Library
Standard Packages Elaboration

Event driven Simulation

Concurrency Concurrent bodies Sequentiality

 Sequential Bodies VHDL Objects (signals, variables and constants) Real Time Delta Delay Scheduling Resolution Code Formal

VHDL constructs for structures and hierarchy Descriptions

Basic Components:

entity inv is port (i1: in bit; y: out bit); end entity; architecture structure of inv is Y<= not i1 after 3 ns; end structure;