VLSI -‫מבוא ל‬

1 '‫הרצאה מס‬

Introduction, Design Metrics

CMOS Transistor

based on course & book by

Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
and foils from
Mary Jane Irwin
VLSI
‫מבוא‬ ‫אבי‬
 ‫סילבוס‬

‫שיקולי תכנון ומטדולוגיות‬ ‫מטרת הקורס‪:‬הכרת מעגלי‬

‫בתכנון רכיבים‬
‫מהלך הקורס‪:‬הקורס בנוי מהרצאות ותרגילים‬
‫תרגילי בית‪:‬במספרחובה להגיש‬
‫בוחן ביניים‪:‬מגן‬
‫קביעת ציון‪:‬בחינה סופיתבוחןתרגילים‬

‫‪VLSI‬‬
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 ‫‪...‬סילבוס המשך‬

‫‪VLSI‬‬
‫מבוא‬ ‫אבי‬
Transistor Revolution

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VLSI
‫מבוא‬ ‫אבי‬
The Transistor Revolution

First transistor
Bell Labs,
1948

VLSI
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The First Integrated Circuits

Bipolar
logic

ECL 3-input Gate

Motorola 1966

VLSI
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MOSFET Technology
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VLSI
‫מבוא‬ ‫אבי‬
Moore’s Law
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VLSI
‫מבוא‬ ‫אבי‬
Moore’s Law in Microprocessors
Transistors on lead microprocessors double every 2 years

1000

100
2X growth in 1.96
years!
10
P
Pentium®
6
Transistors

1 486 proc
386
(MT)

0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
VLSI
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Intel 4004 Microprocessor

VLSI
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Intel Pentium (IV) Microprocessor

VLSI
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State-of-the Art: Lead Microprocessors

VLSI
‫מבוא‬ ‫אבי‬
Evolution in DRAM Chip Capacity
human
memory
human DNA
4X growth every 3 years! 




b 
ook





2 hrs CD audio
 30 sec HDTV


p
age

VLSI
‫מבוא‬ ‫אבי‬
Die Size Growth

100

P6
486 Pentium ®
10 proc
Die size

386
286
(mm)

8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10
years
1
1970 1980 1990 2000 2010
Year
VLSI
‫מבוא‬ ‫אבי‬
Clock Frequency
Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years Power-limited

frequency increase
P6
100
Pentium ®
Frequency

486 proc
10 8085 386
8086 286
(Mhz)

1 8080
8008
4004
0.
1
1970 1980 1990 2000 2010
Year
VLSI
‫מבוא‬ ‫אבי‬
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
1000 500W
Pentium®
100 proc
(Watts)
Power

286 486
10 8086 386
8085
8080
8008
1 4004

0.
1 1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be
prohibitive

VLSI
‫מבוא‬ ‫אבי‬
Power density

10000
Rocket
Nozzl
1000
e
Nuclea
Power Density

rReactor
100
(W/cm2)

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium®
8080 286 486 proc
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low

temp

VLSI
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Design Productivity Trends
10,00 100,00

Logic Tr./Chip 10,00

(M

1,00
)

Tr./Staff Month.

(K) Trans./Staff - Mo.

10 1,00
Complexit
Logic Transistor per

Productivity
1 58%/Yr. compounded 10
y

Complexity growth

1 1

x x
0. 1
xx 21%/Yr. compound
Chip

x x x
x Productivity growth
0 0.

0.00 0
989

003

005
991

993

995
997

999

001
985

987

007
981

983

009
1

2
1

1
1

2
1

2
1

2
Complexity outpaces design productivity

VLSI
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Technology Directions: SIA Roadmap

VLSI
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Why Design Methods?

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VLSI
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Design Abstraction Levels

SYSTE
M

MODULE

GATE

CIRCUIT

DEVIC
E

VLSI
‫מבוא‬ ‫אבי‬
Major Design Challenges
● ●
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VLSI
‫מבוא‬ ‫אבי‬
Design Metrics

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VLSI
‫מבוא‬ ‫אבי‬
Cost of Integrated Circuits
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-
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VLSI
‫מבוא‬ ‫אבי‬
Silicon Wafer

VLSI
‫מבוא‬ ‫אבי‬
Variable Costs







VLSI
‫מבוא‬ ‫אבי‬
Yield Example

● 
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●

q l

VLSI
‫מבוא‬ ‫אבי‬
Examples of Cost Metrics (1994)

VLSI
‫מבוא‬ ‫אבי‬
Reliability
Noise in Digital Integrated Circuits

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VLSI
‫מבוא‬ ‫אבי‬
Example of Capacitive Coupling
q Signal wire glitches as large as 80% of the supply voltage will
be common due to crosstalk between neighboring wires as
feature sizes continue to scale

Crosstalk vs. Technology

VLSI
‫מבוא‬ ‫אבי‬
Static Gate Behavior
q static behavior
q 
q nominal voltage level


q signal swing

VLSI
‫מבוא‬ ‫אבי‬
DC Operation
Voltage Transfer Characteristics (VTC)

Switching
Threshold

VLSI
‫מבוא‬ ‫אבי‬
Mapping Logic Levels to the Voltage Domain
q

"1"

Undefine
d
Region

"0"

VLSI
‫מבוא‬ ‫אבי‬
Noise Margins

"1
"

Noise Margin Undefine

High d
Noise Margin Region
Low

"0
"

Gate Gate
Output Input

VLSI
‫מבוא‬ ‫אבי‬
Noise Immunity

q Noise immunity
q

VLSI
‫מבוא‬ ‫אבי‬
Directivity

q undirectional
● full

q output impedanceinput impedance

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VLSI
‫מבוא‬ ‫אבי‬
Fan-In and Fan-Out

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VLSI
‫מבוא‬ ‫אבי‬
The Ideal Inverter
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●





VLSI
‫מבוא‬ ‫אבי‬
The Ideal Inverter
●
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●


g=-
 

VLSI
‫מבוא‬ ‫אבי‬
Design Metrics

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VLSI
‫מבוא‬ ‫אבי‬
Delay Definitions

Vi V
out

Vi

V
out

VLSI
‫מבוא‬ ‫אבי‬
Delay Definitions

Vi V
out

Vi

tp = (tpHL +

t
t t
V pHL pLH

out

t
t t
f r
VLSI
‫מבוא‬ ‫אבי‬
Modeling Propagation Delay










VLSI
‫מבוא‬ ‫אבי‬
Power and Energy Dissipation

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VLSI
‫מבוא‬ ‫אבי‬
Power and Energy Dissipation
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VLSI
‫מבוא‬ ‫אבי‬
Summary

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VLSI
‫מבוא‬ ‫אבי‬
 CMOS Transistor

VLSI
‫מבוא‬ ‫אבי‬
Review: Design Abstraction Levels

SYSTE
M

MODULE

GATE

CIRCUIT

DEVIC
E

VLSI
‫מבוא‬ ‫אבי‬
The MOS Transistor

Polysilicon or Metal
Aluminum or
Copper

VLSI
‫מבוא‬ ‫אבי‬
The NMOS Transistor Cross Section

VLSI
‫מבוא‬ ‫אבי‬
Switch Model of NMOS Transistor

VLSI
‫מבוא‬ ‫אבי‬
The PMOS Transistor Cross Section

VLSI
‫מבוא‬ ‫אבי‬
Switch Model of PMOS Transistor

VLSI
‫מבוא‬ ‫אבי‬
Threshold Voltage Concept

VLSI
‫מבוא‬ ‫אבי‬
The Threshold Voltage
q


q 
q

VLSI
‫מבוא‬ ‫אבי‬
Transistor in Linear Mode

VLSI
‫מבוא‬ ‫אבי‬
Voltage-Current Relation: Linear Mode
q 







VLSI
‫מבוא‬ ‫אבי‬
The Body Effect

●
●

VLSI
‫מבוא‬ ‫אבי‬
Transistor in Saturation Mode

VLSI
‫מבוא‬ ‫אבי‬
Voltage-Current Relation: Saturation Mode

q 

q 

VLSI
‫מבוא‬ ‫אבי‬
Current Determinates
q
●
●
●
● 
●
- 
- 

VLSI
‫מבוא‬ ‫אבי‬
Long Channel I-V Plot (NMOS)

VLSI
‫מבוא‬ ‫אבי‬
Short Channel I-V Plot (NMOS)

VLSI
‫מבוא‬ ‫אבי‬
Short Channel I-V Plot (PMOS)

VLSI
‫מבוא‬ ‫אבי‬
Unified Transistor model for manual analysis

Note:

VLSI
‫מבוא‬ ‫אבי‬
Unified model vs separate models
By definition VGT == VGS – VT , remember this wile looking at equations below
Case 1: Vmin = VGT, Saturation

Case 2: Vmin = VDS , Linear

Case 3: Vmin = VDSAT , Velocity

saturation

remember k’n =

VLSI
‫מבוא‬ ‫אבי‬
Boundaries of operation for Unified Model

VLSI
‫מבוא‬ ‫אבי‬
 Summary of MOSFET Operating Regions

q VGS > VT
● LinearVDS < VDSAT
● Saturated VDS  VDSAT

q Sub-ThresholdVGS VT
● VGS VDS

VLSI
‫מבוא‬ ‫אבי‬
Other MOS Transistor Concerns
q 
q
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q
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q
●
q

VLSI
‫מבוא‬ ‫אבי‬
Present and Future Perspectives

25 nm FINFET MOS
VLSI
‫מבוא‬ ‫אבי‬