Introduction to Simulation of

Verilog Designs
using ModelSim-Altera
Presenter: Phong Bui

Email: phongbui102@gmail.com
Digital Image Processing Group IC Design Lab Hanoi 29/01/2013

Contents

1. Introduction

2. Design Project

3. Simulate without testbench

4. Simulate with testbench

1. Introduction
ModelSim is a verification and simulation tool for

VHDL, Verilog, SystemVerilog, and mixedlanguage designs.

Software : ModelSim-Altera 6.6d Starter Edition

References :
Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform Editor (Altera). ModelSim Tutorial (Mentor Graphics).
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Contents

1.Introduction

2.Design Project

3.Simulate without testbench

4.Simulate with testbench

2. Design Project
Simple example : f(x1, x2, x3) = x1x2 + x2x3 + x3x1 Verilog code :
module majority(x1, x2 ,x3 ,f); input : x1, x2, x3; output: f;

assign f = (x1&x2)|(x2&x3)|(x3&x1);
endmodule;
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2. Design Project
Open the ModelSim simulator. In the displayed window select File > New > Project

2. Design Project
A Create Project pop-up box will appear
1.Enter the name of the project

Choose Project Location

2. Design Project
Create new file

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2. Design Project

Double click

Text Editor

2. Design Project
Or add existing file

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2. Design Project
After completed coding, select Compile > Compile all

Compile of majority.v was successfull

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Contents

1.Introduction

2.Design Project

3.Simulate without testbench

4.Simulate with testbench

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3. Simulate without testbench

Select Simulate > Start simulation, Start Simulation window will appear

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3. Simulate without testbench

Simulation window

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3. Simulate without testbench

Create waveforms for Simulation

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3. Simulate without testbench

Modify waveforms for Simulation
Right click

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3. Simulate without testbench

Waveform window

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3. Simulate without testbench

Waveform window

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3. Simulate without testbench

With output signal

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3. Simulate without testbench

SimulateSelect Run all

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3. Simulate without testbench

Result

To stop simulation, slect Simulate > End simulation

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Contents

1.Introduction

2.Design Project

3.Simulate without testbench

4.Simulate with testbench

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4. Simulate with testbench

Create testbench file to project

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4. Simulate with testbench

After completed coding, select Compile > Compile all

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4. Simulate with testbench

Select Simulate > Start simulation

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4. Simulate with testbench

Add signal to waveform

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4. Simulate with testbench

Add signal to waveform

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4. Simulate with testbench

Simulate

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4. Simulate with testbench

Zoom in, zoom out

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Demo

Question ?

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