BJTs amplifier requires a knowledge of both the DC analysis

(large signal) and AC analysis (small signal).

BJT need to be operate in active region used as amplifier.
The cutoff and saturation region used as a switches.
For the BJTs to be biased in its linear or active operating
region the following must be true:
a) BE junction forward biased, 0.6 or 0.7V
b) BC junction reverse biased
DC bias analysis assume all capacitors are open circuit.
For transistor amplifiers the resulting DC current and voltage
establish an operating point that define the region that can be
employed for amplification process.

Important basic relationships for a transistor:
V
BE
=0.7V
I
E
=(+1)I
B
I
C
I
C
= I
B
Operating point quiescent point or Q-point
The biasing circuit can be designed to set the device operation at
any of these points or others within the active region.
The BJT device could be biased to operate outside the max limits,
but the result of such operation would be shortening of the
lifetime of the device or destruction of the device.
The chosen Q-point often depends on the intended use of the
circuit.
replace the capacitors with an open-circuit equivalent because
the reactance of a capacitor for dc is
The dc supply V
cc
can be separated into two supplies
Fixed bias circuit
DC equivalent
B
BE CC
B
R
V - V
I =
Write KVL equation in the
clockwise direction of the loop :
+V
CC
I
B
R
B
V
BE
=0

Solving the equation for the
current I
B
results :

Base-emitter loop
B
BE cc
B
R
V V
I

=
The magnitude of the I
C
is related directly
to IB through
I
C
=I
B
Apply KVL in the clockwise direction
around the indicated close loop results:
V
CE
+I
C
R
C
-V
CC
=0
V
CE
= V
CC
-I
C
R
C
Recall that :
V
CE
= V
C
- V
E
In this case, V
E
= 0V, so
V
CE
=V
C

V
BE
=V
B
-V
E
Than V
E
=0V, V
BE
=V
E
Collectoremitter loop
Determine the following for the fixed bias configuration
a) I
BQ
and I
CQ
b) V
CEQ
c) V
B
and V
C
d) V
BC
Determine the following for the fixed bias configuration
a) I
BQ
and I
CQ
b) V
CEQ
c) V
B
d)V
C
e) V
E
( )( )
( )( )
V 0 V ) e
V 8.17 V V d)V
V 0.7 V V ) c
V 17 . 8
k 7 . 2 2.93m - 16
R I - V V ) b
mA 93 . 2 u 55 . 32 90 I I
uA 55 . 32
k 470
7 . 0 16
R
V V
I ) a
E
C CEQ CE
B BE
C C CC CEQ
BQ CQ
B
BE CC
BQ
=
= = =
= =
=
=
=
= = | =
=

=
The term saturation is applied to any system where levels have reached
their max values.
For a transistor operating in the saturation region, the current is
maximum value for a particular design.
Saturation region are normally avoided because the B-C junction is no
longer reverse-biased and the output amplified signal will be distorted.

By referring to example 1 and the figure, determine the
saturation level.

Solution


limit. the
within operates is I that the concluded be can
It . mA 34 . 2 I in 1 example of design The
mA 45 . 5
k 2 . 2
12
R
V
I
CQ
CQ
C
CC
Csat
=
= = =
Find the saturation current for the fixed-bias configuration of
figure example 2.

Solution

limit. the
within operates is I that the concluded be can
It . mA 93 . 2 I in 2 example of design The
mA 92 . 5
k 7 . 2
16
R
V
I
CQ
CQ
C
CC
Csat
=
= = =
We investigate how the network parameters define the possible
range of Q-points and how the actual Q-point is determined.
Refer to figure below (output loop) one straight line can be draw
at output characteristics. This line is called load line.
This line connecting each separate of Q-point.
At any point along the load line,
values of I
B
, I
C
and V
CE
can be picked
off the graph.
The process to plot the load line
as follows:
Step 1:
Refer to circuit, V
CE
=V
CC
I
C
R
C
(1)
Choose I
C
= 0 mA. Subtitute into (1), we get
V
CE
=V
CC
(2) located at X axis
Step 2:
Choose V
CE
=0V and subtitute into (1), we get
I
C
=V
CC
/R
C
(3) located at Y-axis
Step 3:
Joining two points defined by (2) + (3), we get straight line that
can be drawn as Fig.

Load-Line Analysis
Case 1:
Level I
B
changed by varying the value of R
B
.
Q-point moves up and down
Case 2:

V
CC
fixed and R
C
change
the load line will shift as
shown in Fig 5.8

I
B
fixed, the Q-point will
move as shown in the same
figure.
Load-Line Analysis
Case 3:

R
C
fixed and V
CC
varied,
the load line shifts as
shown in Fig.
Given the load line of Fig. 5.10 and defined Q-point, determine the
required values of V
CE
, R
C
and R
B
for a fixed bias configuration.

kohm 2311
17
7 . 0 40
I
V V
R
R
V - V
I
kohm 67 . 2
m 15
40
I
V
R
0V. V at
R
V
I
mA 0 I at V 40 V V
B
BE CC
B
B
BE CC
B
C
CC
C
CE
C
CC
C
C CC CE
: 2 Step
: 1 Step
=

=
=
= = =
= =
= = =
Determine the value of Q-point for this figure. Also find the new value
of Q-point if | change to 150.

The DC bias network below contains an emitter resistor to
improve the stability level of fixed-bias configuration.
The analysis consists of two scope:
- Examining the base-emitter loop (input loop)
- Use the result to investigate the collector-emitter loop (output
loop)

For the emitter-bias network for Fig.4.22 determine:
a)I
B
b)I
C
c)V
CE
d)V
C
e)V
E
f )V
B
g)V
BC


( ) ( )
( )( )
( )
( )( )
( )( )
( )( )
required) as biased (reverse
V 27 . 13 98 . 15 71 . 2 V V V ) g
V 71 . 2 01 . 2 7 . 0 V V V ) f
V 01 . 2 k 1 m 01 . 2 R I R I V
OR
V 01 . 2 97 . 13 98 . 15 V V V ) e
V 98 . 15 02 . 4 20
k 2 m 01 . 2 20 R I V V ) d
V 97 . 13
03 . 6 20 k 1 k 2 m 01 . 2 20
R R I - V V c)
mA 01 . 2 1 . 40 50 I I b)
A 1 . 40
k 1 1 50 k 430
7 . 0 20
R 1 R
V - V
I a)
C B BC
E BE B
E C E E E
CE E E
C C CC C
E C C CC CE
B C
E B
BE CC
B
= = =
= + = + =
= = ~ =
= = =
= =
= =
=
= + =
+ =
= = | =
=
+ +

=
+ | +
=
The saturation current for an emitter-bias configuration is:

Determine the saturation current for the network of example 7.

Solution:







This value is about three times the level of I
CQ
(2.01mA |=50)
for the example 7. Its indicate the parameter that been used in
example 7 can be use in analysis of emitter bias network.
mA 67 . 6
k 3
20
k 1 k 2
20
R R
V
I
E C
CC
Csat
= =
+
=
+
=
Step 3:
Joining two points defined by (2) + (3), we get straight line that can
be drawn as Fig. 5.17:
Load-Line Analysis
I
CQ
and V
CEQ
from the table is changing dependently the changing
of |.
The voltage-divider bias configuration is designed to have a less
dependent or independent of the |.
If the circuit parameter are properly chosen, the resulting levels of
I
CQ
and V
CEQ
can be almost totally independent of |.

| I
B
(A) I
C
(mA) V
CE
(V)
50 40.1 2.01 13.97
100 36.3 3.63 9.11
Two method for analyzed
the voltage-divider bias
configuration:
- Exact method
- Approximate method

Step 1:
The input side of the
network can be redrawn
for DC analysis.
Step 2:
Analysis of Thevenin
equivalent network to the
left of base terminal

Step 2(a):
Replaced the voltage sources
with short-circuit equivalent
and gives the value of R
TH

2 1 R R RTH =
Step 2(b):
Determining the E
TH
by replacing the voltage sources and
open circuit Thevenin voltage. Then apply the voltage-
divider rule.

2 1
CC 2
2 R TH
R R
V R
V E
+
= =
Step 3:
The Thevenin network is then redrawn and I
BQ
can be
determined by KVL

0 = E E BE TH B TH R I V R I E
( ) gives I 1 I Subtitute B E + =
( ) E TH
BE TH
B
R 1 R
V E
I
+ | +

=
Determine the DC bias voltage V
CE
and current I
C
for the
voltage-divider configuration of network below:

47
49
( )
kohm 3.55
k 9 . 3 k 39
k 9 . 3 k 39
R R R 2 1 TH
=
+
=
=
( )
V 2
k 9 . 3 k 39
22 k 9 . 3
R R
V R
E
2 1
CC 2
TH =
+
=
+
=
( )
( )
A 05 . 6
k 5 . 1 1 140 k 55 . 3
7 . 0 2
R 1 R
V E
I
E TH
BE TH
B
=
+ +

=
+ | +

=
( ) mA 85 . 0 05 . 6 140 I I B C = = | =
( )
( )
V 22 . 12
k 5 . 1 k 10 m 85 . 0 22
R R I V V E C C CC CE
=
+ =
+ =
For the voltage-
divider bias
configuration,
determine:
I
BQ
, I
CQ
, V
CEQ
, V
C
, V
E
and
V
B
.

( )
kohm 7.93
k 1 . 9 k 62
k 1 . 9 k 62
R R R 2 1 TH
=
+
=
=
( )
V 05 . 2
k 1 . 9 k 62
16 k 1 . 9
R R
V R
E
2 1
CC 2
TH =
+
=
+
=
( )
( )
A 4 . 21
k 68 . 0 1 80 k 93 . 7
7 . 0 05 . 2
R 1 R
V E
I
E TH
BE TH
BQ
=
+ +

=
+ | +

=
( ) mA 712 . 1 4 . 21 80 I I B CQ = = | =
( )
( )
V 16 . 8
k 68 . 0 k 9 . 3 m 712 . 1 16
R R I V V E C C CC CEQ
=
+ =
+ =
( ) V 32 . 9 k 9 . 3 m 712 . 1 16
R I V V C C CC C
= =
=
( )
( )
V 18 . 1
k 68 . 0 m 712 . 1 4 . 21
k 68 . 0 I I
R I V
C B
E E E
=
+ =
+ =
=
V 88 . 1
7 . 0 18 . 1
V V V BE E B
=
+ =
+ =
Solution
Step 1:
|R
E
> 10R
2

Step 2:
The input section can be represented by the network of figure below and
R
2
can be considered in series by assuming
I
1
~I
2
and I
B
= 0A .

( )
( ) E i
i
R R
I I R R
1
2 1 2
+ =
~ >>
|
This eqn must be satisfied. If not, approximate analysis
cant be used , and you have to use the exact analysis
(Thevenins method)
2 1
CC 2
R2 B
R R
V R
V V
: determined be can voltage base The
+
= =
BE E
E B BE
E
V - V V
V - V V
: well as calculated be can V level and
B =
=
E CQ
E
E
E I I and
R
V
I
: determined be can
current emitter the and
~ =
E E
R R ) 1 ( R where
10R R
: approach e approximat
define that will Condition
i
2 E
| | = + =
>
Step 3:
Repeat the analysis of example 9 using the approximate
technique and compare solution for I
CQ
and V
CEQ
.

Solution:

( )( ) ( )
! satisfied kohm 39 kohm 210
k 9 . 3 10 k 5 . 1 140
R 10 R
: Step1
2 E
>
>
> |
drawn be can cct bias partial the
: 2 Step

( )
V 2
k 9 . 3 k 39
22 k 9 . 3
R R
V R
V
: 3 Step
2 1
CC 2
B =
+
=
+
=
V 3 . 1 7 . 0 2
V V V BE B E
= =
=
mA 867 . 0
k 5 . 1
3 . 1
R
V
I I
E
E
E CQ = = = ~
( )
( )
V 03 . 12
k 5 . 1 k 10 m 867 . 0 22
R R I V V E C C CC CEQ
=
+ =
+ =
I
CQ
(mA) V
CEQ
(V)
Exact
Analysis
0.85 12.22
Approximate
Analysis
0.867 12.03
I
CQ
and V
CEQ
are certainly close.
Repeat the exact analysis of example 9 if | is reduced to 70.
Compare the solution for I
CQ
and V
CEQ
.

Solution:



kohm 3.55 RTH =
V 2 ETH =
( )
( )
A 81 . 11
k 5 . 1 1 70 k 55 . 3
7 . 0 2
R 1 R
V E
I
E TH
BE TH
B
=
+ +

=
+ | +

=
( ) mA 83 . 0 81 . 11 70 I I B C = = | =
Example
( )
( )
V 46 . 12
k 5 . 1 k 10 m 83 . 0 22
R R I V V E C C CC CE
=
+ =
+ =
|
I
CQ
(mA) V
CEQ
(V)
140 0.85 12.22
70 0.83 12.46
Conclusion: Even though | is drastically half, the level I
CQ

and V
CEQ
are essentially same.
Solution (continued)
Determine the levels of I
CQ
and V
CEQ
for the voltage-divider
configuration using the exact and approximate analysis.
Compare the solution.
Example
Solution
( )
kohm 35 . 7 1
k 22 k 82
k 22 k 82
R R R
: Analysis Exact
2 1 TH
=
+
=
=
( )
V 81 . 3
k 22 k 82
18 k 22
R R
V R
E
2 1
CC 2
TH =
+
=
+
=
( )
( )
A 6 . 39
k 2 . 1 1 50 k 35 . 17
7 . 0 81 . 3
R 1 R
V E
I
E TH
BE TH
BQ
=
+ +

=
+ | +

=
( ) mA 98 . 1 6 . 39 50 I I B CQ = = | =
( )
( )
V 54 . 4
k 2 . 1 k 6 . 5 m 98 . 1 18
R R I V V E C C CC CEQ
=
+ =
+ =
( )( ) ( )
satisfied) (not 220kohm 60kohm
k 22 10 k 2 . 1 50
R 10 R
: Analysis e Approximat
2 E
>/
>
> |
( )
V 81 . 3
k 22 k 82
18 k 22
R R
V R
E V
2 1
CC 2
TH B =
+
=
+
= =
V 11 . 3 7 . 0 81 . 3
V V V BE B E
= =
=
mA 59 . 2
k 2 . 1
11 . 3
R
V
I I
E
E
E CQ = = = ~
( )
( )
V 88 . 3
k 2 . 1 k 6 . 5 m 59 . 2 18
R R I V V E C C CC CEQ
=
+ =
+ =
Solution (continued)
Solution (continued)
I
CQ
(mA) %difference V
CEQ
(V) %difference
Exact
Analysis
1.98
23.5%
4.54
17%
Approximate
Analysis
2.59 3.88
The saturation collector-emitter circuit for the voltage-divider
configuration has the same appearance as the emitter-biased
configuration as shown below.
E C
CC
Csat
R R
V
I
+
=
The similarities with the output circuit of the emitter-biased
configuration result in the same intersections for the load line of the
voltage-divider configuration.

The load line therefore have the same appearance with:
axis Y at located
R R
V
I 0V VCE
E C
CC
C
+
= =
axis X at located V V 0mA IC CC CE = =
Another way to improve the stability of a bias circuit is to add a feedback
path from collector to base. In this bias circuit the Q-point is only slightly
dependent on the transistor Beta |.
Applying Kirchoffs voltage law:
V
CC
I
C
'R
C
I
B
R
B
V
BE
I
ERE
= 0
Note: I
C
' = I
C
+ I
B
-- but usually I
B
<< I
C
so I
C
' ~ I
C

Knowing I
C
= |I
B
and I
E
~ I
C
then:
V
CC
|I
B
R
C
I
B
RB V
BE
|I
B
R
E
= 0
Simplifying and solving for I
B
:



) R (R R
V V
I
E C B
BE CC
B
+ +

=
|
Applying Kirchoffs voltage law: I
E
R
E
+ V
CE
+ I
C
'R
C
V
CC
= 0

Since I
C
' ~ I
C
and I
C
= |I
B
: I
C
(R
C
+ R
E
) + V
CE
V
CC
=0

Solving for V
CE
: V
CE
= V
CC
- I
C
(R
C
+R
E
)

) (
E C C CC CE
R R I V V + =
Transistor Saturation Level
E C
CC
C C
R R
V
max I sat I
+
= =
Load Line Analysis
It is the same analysis as for the voltage divider bias
and the emitter-biased circuits.
For the collector
feedback configuration,
determine
IB
IC
VC

(a) I
B
=

= 15.88 A

(b) I
C
= |I
B
= (120)(15.88 A)
= 1.91 mA

(c) V
C
= V
CC
I
C
R
C

= 16 V (1.91 mA)(3.6 kO)
= 9.12 V

16 V 0.7 V
( ) 470 k + (120)(3.6 k 0.51 k )
CC BE
B C E
V V
R R R |

=
+ + O O+ O
We are able to design the transistor circuit using the ideas
that we have learnt before during analyzing dc biasing
circuit.
How?
- Understand the Kirchoffs Law and other electric
circuit law such as Ohms Law, Thevenin Laws etc
- Identify the parameters given
- Analyze into the input/output for the system and build
a loop using electric circuits law.

If the transistor and supplies are specified, the design
process will simply determine the required resistor for
a particular design.
Once the theoretical values of the resistors are
determined, the nearest standard commercial values
are normally chosen and any variations due to not
using the exact resistance values are accepted as part of
the design.
R
unknown
=V
R
/I
R
Given the device characteristics in figure, determine
V
cc
, R
B
and R
C
for the fixed-bias configuration.
Given that ICQ = 2 mA and VCEQ = 10V, determine R1
and RC for the network
The emitter resistor is to
1/10 of the supply voltage
R
E
and R
C
cannot proceed directly from the information
just specified.
R
E
to provide dc bias stabilization so that the change of
collector current due to leakage currents in the transistor
and the transistor beta would not cause a large shift in
the operating point.
The R
E
cannot be unreasonably large because the voltage
across it limits the range of swing of the voltage from
collector to emitter.
V
E
typically -1/10 from supply voltage
Determine the resistor values for the network, for the
indicated operating point and supply voltage.
Use VE = 1/10 VCC
The emitter resistor is to 1/10
of the supply voltage
To determine R
1
and R
2
use
10R
2
R
E

Design a voltage divider bias network using a supply of
24V, a transistor with = 110, and an operating point of
ICQ = 4 mA and VCEQ = 8 V. choose VE = 1/8 VCC. Use
standard value.
R
E
= = 0.75 kO

R
C
=

= = 3.25 kO

V
B
= V
E
+ V
BE
= 3 V + 0.7 V = 3.7 V
V
B
= 2 unknowns!

use |R
E
> 10R
2
for increased stability
( )
Q
C
CC CE E
R
CC C
C C C
V V V
V
V V
I I I
+

= =
3 V
4 mA
E E
E C
V V
I I
~ =
24 V (8 V + 3 V) 24 V 11 V 13 V
4 mA 4 mA 4 mA

= =
2 2
2 1 2 1
(24 V)
3.7 V =
CC
R V R
R R R R

`
+ +
)
(110)(0.75 kO) = 10R
2

R
2
= 8.25 kO
Choose R
2
= 7.5 kO
Substituting in the above equation:
3.7 V =

R
1
= 41.15 kO
Standard values:
R
E
= 0.75 kO, R
C
= 3.3 kO, R
2
= 7.5 kO, R
1
= 43 kO


1
7.5 k (24 V)
7.5 k R
O
O+
Transistor works as an inverter in computer circuits.
Operating point switch from cut-off to saturation along the
load line for proper inversion.
In order to understand, we assume that;
I
C
=I
CEO
=0mA when IB = 0A
V
CE
=V
sat
=0V
One must understand the transistor graph output and
load-line analysis to describe and discuss about the
transistor switching networks.
uA
mA I
I Theref ore
mA
R
V
k
V
I
I
I
Csat
B
C
cc
I
B
Csat
B
8 . 48
125
1 . 6
,
1 . 6 I
63uA
68
7 . 0
that, see ll we' figure, with the compare
that ensure must We
Csat
= = >
= =
=

=
>
|
|
How to define and encounter transistor circuit problem?