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Architecture
Programmable
interconnect
Dedicated
multipliers
Configurable
Logic Blocks
(CLBs)
• Virtex™-II
architecture’s core Clock Management
voltage (DCMs, BUFGMUXes)
operates at 1.5V
Basic FPGA Architecture 2 - 5 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Overview
• Slice Resources
• I/O Resources
• Memory and
Clocking
• Spartan-3, Spartan-
3E, and Virtex-II Pro
Features
• Virtex-4 Features
• Summary
• Appendix
Basic FPGA Architecture 2 - 6 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Slices and CLBs
• Each Virtex-II CLB COUT COUT
BUFT
contains BUF T
four slices Slice S3
– Local routing provides
feedback between slices
Slice S2
in the same CLB, and it Switch SHIFT
provides routing to Matrix
neighboring CLBs
Slice S1
– A switch matrix provides
access
Slice S0
to general routing Local Routing
resources
CIN CIN
vertically,
up only
CLR
– Two independent
carry
chains per CLB
Basic FPGA Architecture 2 - 8 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Detailed Slice Structure
• The next few slides
discuss the slice
features
– LUTs
– MUXF5, MUXF6,
MUXF7, MUXF8
(only the F5 and
F6 MUX are shown
in this diagram)
– Carry Logic
– MULT_ANDs
– Sequential
Elements
F8
two MUXF7 outputs
F5
(from the CLB above
Slice S3 or below)
MUXF6 combines
F6
slices S2 and S3
F5
Slice S2
two MUXF6
Slice S1
F5
outputs
MUXF6 combines slices S0 and S1
F6
Slice S0
F5
A S CO
DI
CY_MUX
CI
CY_XOR
MULT_AND
AxB
LUT
B LUT
input D PRE Q
CE
• Separate set and reset CLR
controls
– Can be synchronous or LDCPE
asynchronous D PRE Q
CE
• All controls are shared G
shift registers
• Dedicated connection
from Q15 to D input of
the next SRL16CE LUT D Q
CE
– Shift register length can
A[3:0]
be changed Q15 (cascade out)
asynchronously
by toggling address A
Basic FPGA Architecture 2 - 15 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Shift Register LUT Example
• The SRL can be used to create a No Operation (NOP)
– This example uses 64 LUTs (8 CLBs) to replace 576
flip-flops (72 CLBs) and associated routing and delays
12 Cycles
Operation A Operation B
64
4 Cycles 8 Cycles
64
Operation C Operation D -
NOP
3 Cycles 9 Cycles
Paths are Statically
Balanced
12 Cycles
memory WE
WCLK
• Synchronous write LUT A0
A1
O
A2
• Asynchronous read A3
– Accompanying flip-flops
can be used to create D
RAM32X1S
D
RAM16X1D
synchronous read WE
WCLK
WE
WCLK
Slice
• RAM and ROM are A0
A1
O A0
A1
SPO
RAM LUT
after configuration
• Emulated dual-port RAM
– One read/write port
– One
Basic FPGA Architecture 2 - 23
read-only port
© 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Block SelectRAM Resources
• Up to 3.5 Mb of RAM in 18-kb block SelectRAM memory
18-kb blocks DIA
DIPA
– Synchronous read and ADDRA
write WEA
ENA
• True dual-port memory SSRA DOA
CLKA DOPA
– Each port has
synchronous read and DIB
DIPB
write capability ADDRB
WEB
– Different clocks for each ENB
port SSRB DOB
CLKB DOPB
• Supports initial values
• Synchronous reset on
output latches
• Supports parity bits
Basic FPGA Architecture 2 - 24 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Dedicated Multiplier Blocks
• 18-bit twos complement signed operation
• Optimized to implement Multiply and Accumulate
functions
• Multipliers are physically located next to block
SelectRAM™ memory
Data_A
(18 bits) 4x4
signed
8x8
18 x 18 Output
Multiplier (36 bits) signed
12 x 12
signed
18 x 18
Data_B signed
(18 bits)
– Similar to the
Virtex™-II Slice X1Y1
– Right-hand SLICEL
(Logic) SHIFTOUT CIN
CIN
• Application Notes
– www.xilinx.com → Documentation → Application
Notes
• Education resources
– Designing with the Virtex-4 Family course
– Spartan-3E Architecture free Recorded e-Learning
D1
Clock Reg DDR MUX OBUF
OCK1
PAD
D2
Reg
OCK2 FDDR
• Independent Port A: 8
IN 8 bit
configurations on ports bits
A and B
– Supports data-width OUT 32 bit
Port B: 32
conversion, including bits
parity bits
Basic FPGA Architecture 2 - 43 © 2005 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Clock Buffer Configurations
• Clock buffer (BUFG)
– Low-skew clock distribution
I O
BUFG
• Clock enable buffer (BUFGCE)
– Holds the clock output Low
when Clock Enable (CE) is
I O
inactive BUFGCE
– CE can be active-High or
active-Low CE
– Changes in CE are only
recognized when the clock
input is Low to avoid glitches
and short clock pulses
BUFGMUX
– Switches from one O
I1
clock to another,
glitch-free S
– After a change on
S, the BUFGMUX
S
waits for the Wait for low
currently selected I0