NETWORK SYNCHRONIZATION

AN INTRODUCTION

CONTENT
Introduction Synchronization strategy Timing principles Standards for Synchronization

MODULE OVERVIEW
Goal of Network synchronization Problem Identification Why Network synchronization ? Impact of poor Synchronization

WHAT DOES SYNCHRONIZATION MEANS ?

Derived from Greek Word SUNKHRONOS SUN = Same KHRONOS = Time

Goals of a synchronization system

Maintain network frequency within the performance boundary Know when the network is drifting beyond the boundary |Isolate problems BEFORE they degrade network performance
Primary Reference clock Performance limit

WHY NETWORK SYNCHRONIZATION ?

To transport bits across a network or multiple networks,as well as national boundaries,without losing bits.

Technical
1. Minimize data loss. 2. Increase speed.

Political
1. Comply with standards

Overall
1. Deliver superior quality telecom services.

WHY NETWORK SYNCHRONIZATION ?

Network Element - Clock signals are degraded as they are transported through Network Elements. - There is a large requirement for interconnecting networks for the above reason which makes SYNCHRONIZATION a critical part due to problematic pointer adjustments.

SDH SYNCHRONIZATION PROBLEM SDH RINGS & CHAINS

As Timing passes through the SDH chain,phase noise and difference in optical line rate causes timing impairments
that degrades the QOS

SDH RING

SDH RING

SDH RING

SDH RING
SDH RING

SDH RING

SDH SYNCHRONIZATION PROBLEM SDH BACK BONE RINGS

As Timing passes through the SDH chain,phase noise and difference in optical line rate causes timing impairments

SINGLE NATIONAL SDH RING

that degrades the QOS

IMPACT OF THE POOR SYNCHRONIZATION

Technical
1. 2. 3. 4. 5. 6. General Dropped Calls/Loss of links Voice Audible click Facsimile Distortion Data Corruption/Loss/Retransmit time Video Distortion/frozed frames SONET/SDH PDH boundary impairment

Financial
- Customer Increase cost/Customer loss - Operation Increased maintenance costs - Revenue Low revenues

Synchronization Methods
Plesiochronous Master-Slave Mutual Synchronization Distributive method

DOT/BSNL adopted Masterslave/Centralized architecture.

Hirarchical clock distribution

Master-salve principle G.811 PRC Primary reference clock
Slave clock (Transit node clock)
Synchronization Supply Unit

G.812 TNC

G.812 TNC Slave clock

(Local node

clock)

SSU

G.812 LNC

G.812 LNC

G.812 LNC

G.812 LNC

CLOCK QUALITY LEVELS

Clock MSOH S1 Description Type Bits 5-8
ITU PRC TNC LNC SDH Clock 0010 0100 1000 1011 G.811 G.812 Transit G.812 local Internal G.813 clock ETSI QL-PRC QL-SSUT QL-SSUL QL-SEC ANSI Stratum1 1x10-11 ---Strtum2 1x10-8 Stratum3 4.6x10-6

Quality level
QL-level +/- 1x10-11 +/- 1x10-9 +/- 2x10-8 Highest -

+/- 4.6x10-6 -

1111

Do not use

QL-DNU

Lowest

Terms used in NM2100

 A PRC(Primary reference clock) is a stand alone clock and logical function which --is either an autonomous clock or --it accepts synchronization from a radio or satellite signal and performs filtering. A SSU(Synchronization supply unit) is a logical function which: -accepts synchronization inputs from a number of sources; -selects one of the inputs. - Distributed the resultant clock to the other elements within the node. A SEC(SDH equipment clock) is a internal clock of an SDH network elements

Clock Definition for Telecom Sync

Clocks(Oscillator): The internal part of a NE which determines the timing aspects of the output signal of the NE. Clock Accuracy: If the oscillator is not accurate,the clock will gain or loss time relative to the perfect reference depending on the accuracy.

Clock Holdover
An operating condition of a clock which has lost its controlling input and is using stored data,acquired while in normal operation,to control its output. The stored data is averaged to minimize the effects of short-term variations,allowing the normal conditions to be stimulated within specifications.

Clock holdover
An oscillator enters in holdover when it is no longer disciplined Or corrected to the applied reference signal

Holdover terminates when the output of the clock in no longer Controlled by the data stored from a previously connected reference

frequency

Oscillator Disciplined

Oscillator in hold-over mode Time

SYNCHRONIZATION
Synchronization is a process of steering an output to a zero phase with respect to a more stable reference. This implies that the relationship of the signals are of prime importance,and even if the frequencies of the two signals are exactly the same,adjustments may be required if the correct phase relationship has not been achieved.

Frequency

period

period The frequency is the rate of exchange from one leading edge of a Signal to the next.The actual time between the edge is known as the period(1/f) and must stay constant(on the average) to be cosidered as a stable frequency source.A signal with 1 Hertz will have a peroid of 1 second.

Phase

The two signals with identical frequencies that are out of phase with respect to each other.Signal that are out of phase do not typically cause Timing problem unless the phase do changing at a rapid rate(jitter) of there is large,instantaneous phase change(phase hit).

In phase

Changing phase

Sync Signal Impairments

Impairments of sync signal are generally classified as jitter,wonder or phase transients. Jitter: is the short term phase variations of the significant instant of the signal from their ideal positions in time(spectral component>10 Hz). Wander:is a long term phase variations of the significant instant of the signal from their ideal positions in time(<10 Hz).Typically Measured in ns of MTIE and TDEV.

Jitter
High frequency phase changes caused by bit stuffing and a variety of multiplexing schemes. Jitter frequency is > 10 Hz. Jitter amplitude is measured in UI(Unit Intervals). Most Network Elements have the ability to attenuate jitter.

Wander
Low frequency phase changes measured in UI Caused by different propogation speeds associated with transport facilities and change in temperature. Frequency less than 10 Hz. Wander is difficult to attenuate due to the slow of phase change.

JITTER/WANDER

Jitter > 10 Hz

Wonder < 10 Hz

Understanding Slip
Frame slip An E1 has a frame of 125 microseconds.A frame slip occurs when the two clocks in a data transmission path separated in phase by 125 microseconds. Bit slip If two clock in data transmission path separated in phase by more than one bit width,a bit slip is occurs(i.e 488 nenoseconds).

UNDERSTANDING SLIPS
Digital Network Element have buffers for normal jitter and wonder. Input rate departs from output rate exceeds the buffer(S). New data is coming in faster than can be read out - Some new data lost. New data coming slower in slower than rate sent out - Some data sent twice. In either case,data is corrupted. A slip is overflow or underflow of a digital signal buffer.