Beruflich Dokumente
Kultur Dokumente
SANYASI RAO
Assoc. Prof. & HoD
Dept. of ECE
Balaji Institute of Engineering & Sciences Narsampet, Warangal
What is a Combinational circuit? At instant, the output of the logic circuit depends on present inputs.
Design procedure:
1. Identify the number of inputs and outputs required for the design of the circuit. 2. Derive the truth table. 3. Write the expression for the output either in SOP or POS form. 4. Simplify the expression for the output.
ADDERS
Logic circuit which performs the addition of binary numbers Adders of two types: 1. Half Adder (H.A) 2. Full Adder (F.A) Half Adder It is a combinational logic circuit which performs addition of two binary bits.
A
0 0 1 1
B
0 1 0 1
Sum(S)
0 1 1 0
Carry(C)
0 0 0 1
S AB A B C AB
Full Adder
It is a combinational logic circuit which performs addition of three binary inputs.
S A BCin ABC in A BC in ABCin A ( BCin BC in ) A ( BC in BCin ) A( B Cin ) A( B Cin ) A B Cin Cout ABCin A BCin ABC in ABCin Cin ( AB A B ) AB (C in Cin ) Cin ( A B ) AB
Realizing Full Adder with two Half Adders and one OR gate
SUBTRACTORS
Logic circuit which performs subtraction of binary numbers. Subtractors are of two types: 1. Half Subtractor (H.S) 2. Full Subtractor (F.S) Half Subtractor
A D BOUT
A
0 0 1 1
B
0 1 0 1
Difference(D)
0 1 1 0
Borrow(B0)
0 1 0 0
D AB A B B0 AB
Full Subtractor
Combinational circuit which performs subtraction on three binary digits.
A B Bin A 0 0 B 0 0
D ABBin AB B in AB B in ABCin A ( BBin B B in ) A ( B B in BBin ) A( B Bin ) A( B Bin ) A B Bin Bout ABBin AB B in ABBin ABBin Bin ( AB AB) AB ( B in Bin ) Bin ( A B) AB
0
0 1
1
1 0
0
1 0
1
0 1
1
1 0
1
1 1
0
1 1
1
0 1
0
0 1
0
0 1
Realizing Full Subtractor using two Half Subtractors & one OR gate
A Half Subtractor B Bin Half Subtractor D
Bout
Each stage in the parallel adder depends on the previous stage carry. Delay time is additive.
1s Complement Subtractor
It requires two stages of addition. When the end carry is 1, it has to be added with the LSB adder. If the end carry is zero, single stage of addition produces the result but the answer is negative.
2s Complement Adder/Subtractor
Adder
if
M=0
M=1
Subtractor if
When the control input, M is 0 the output of XOR gates are B3B2B1B0 and the circuit functions as a 2s complement adder. When the control input is 1 the output of XOR gates are B3 B2 B1 B0 which is the 1s complement of the subtrahend. Since the control input is 1, the binary 1 is added with the LSB added with B3 B2 B1 B0 which
BCD Adder
A3 C4 F.A S3 F.A S2 F.A H.A B3 A2 B2 A1 B1
A0
B0
S1
F.A
H.A
COUT
S3
S2
S1
S0
The BCD adder requires two stages of addition when the result is greater than 9. the result will be greater than 9, if C4 = 1 or S3S2 = 1 or S3S1 = 1. Therefore the logic expression for these conditions are Y= C4 + S3S2 + S3S1 . if Y=1, binary 6 must be added with S3S2 S1S0 which is performed by the lower stage adders.
One method of speeding up this process by eliminating inter stage carry delay is called look ahead carry addition.
The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propagate and generate logic to make addition much faster.
Ai Bi
Pi
Si
Gi
Ci+1
Ci
Gi is called a carry generate and it produces on carry when both Ai and Bi are 1, regardless of the input carry. Pi is called a carry propagate because it is the term associated with the propagation of the carry from Ci to Ci+1
Gi = Ai.Bi
Pi = (Ai Bi)
C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.C0
Si = Ai Bi Ci = Pi Ci
Since all carries' are dependent on C0 , they can be generated simultaneously and the addition process becomes faster. The hardware required is more. Hence the carry-look ahead adder is expensive compared to parallel adder.
C0 A0 B0
P1
S1
G1
A2 B2
P2
G2
A3 B3 P3 P3 C3 C4 S3 C4
G3
COMPARATORS
A comparator is a logic circuit use to compare the magnitudes of two binary numbers. It provide an output that is active when the two numbers are equal, or additionally provide outputs that signify which of the numbers is greater when equality does not hold. The XNOR gate (coincide gate) is a basic comparator, because its output is a 1 only if its two input bits are equal. Two binary numbers are equal, if and only if all their corresponding bits coincide. For instance, two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 are equal. To implement this logic
Equality ( A3B3 )( A2 B2 )( A1B1 )( A0 B0 )
1 - B i t M a g n i t u d e C o m p a rato r
The logic for a 1-bit comparator: let the 1-bit numbers be A=A0 and B=B0
If A 0 1 and B 0 0, then A B therefore, A B :G A0 B0
A0 0 0 1 1
B0 0 1 0 1
L 0 1 0 0
E 1 0 0 1
G 0 0 1 0
A0
B0
1. If A1 = 1 and B1 = 0, then A > B or 2. If A1 and B1 coincide and A0 = 1 and B1 = 0, then A > B. So the logic for A > B is
A B:G A 1 B1 ( A 1B 1) A 0 B0
1. If A1 = 0 and B1 = 1, then A < B or 2. If AJ1 and B1 coincide and A0 = 0 and B0 = 1, then A < B. So the logic for A < B is
A B : L A1B1 ( A1B1 ) A0 B0
A B : E ( A1B1 )( A0 B0 )
A1 B1 A >B A0 A1 B1 A0 B0 B0 A= B A0 B0 A <B A1
B1
1. If A3 = 1 and B3 = 0, then A > B or 2. If A3 and B3 coincide, and if A2 = 1 and B2 = 0, then A > B or 3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=1 and B2 = 0, then A > B or 4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=1 and B1 = 0, then A > B or So the logic for A > B is
The logic for A < B is: 1. If A3 = 0 and B3 = 1, then A < B or 2. If A3 and B3 coincide, and if A2 = 0 and B2 = 1, then A < B or 3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=0 and B2 = 1, then A < B or 4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=0 and B1 = 1, then A < B or So the logic for A < B is
H. A
H. A
P4
P3
P2
P0
MULTIPLEXERS
A Multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output.
The routing of the desired data input to the output is controlled by SELECT lines.
A MUX selects 1-out-of-N input data sources and transmits the selected data to a single output channel. This is called Multiplexing. MUX is also known as Many to One device.
2n i/p s
2n X n MUX o/p
n select lines
4 X 1 MUX
Y S1 S 0 I0 S1S0 I1 S1 S 0 I 2 S1S0 I3
S1 I0 S1 0 0 1 1 S0 0 1 0 1 Y I0 I1 I2 I3 I3 I1 I2 Y S0
Applications of Multiplexers
1. Data selection 2. Data routing 3. Operation sequencing 4. Waveform generation
Ex:
1
2 3 4 5 6 7 S2 S1 S0 8:1 MUX
Ex:
Step 1: Select the MSB variable as input and the remaining as selector lines variables to the MUX. If the function has n variables, then the size of the required MUX is 2n-1 to 1. Step 2: Draw the truth table for the given function.
Step 3: Complete the function table. a) if both the minterms are circled, apply 1 to the corresponding MUX input. b) if both are not circled, apply 0 to the corresponding MUX input. c) if the top is circled and bottom is not circled, apply A1 to the corresponding MUX input. d) if the top is not circled and bottom is circled, apply A to the corresponding MUX input.
I0 A 0 0 0 0 1 B 0 0 1 1 0 C 0 1 0 1 0 F 0 1 0 1 0 0 1 A A1 A1 A 0 0 4
I1 1 5 1
I2 2 6 A
I3 3 7 A1
I0
I1 I2 4:1 MUX S1 S0 B C
1
1 1
0
1 1
1
0 1
1
1 0
I3
DEMULTIPLEXER
Demultiplexer, DEMUX does the reverse
operation of a MUX. It receives the message over one input line and directs the message to of the many output lines. Hence it known as One to Many device.
1 X 2n i/p
DEMUX
2n o/p s
n select lines
S1 0 0 1 1
S0 0 1 0 1
D 1 1 1 1
Y0 1 0 0 0
Y1 0 1 0 0
Y2 0 0 1 0
Y3 0 0 0 1
S0
S1
Y0 S 1 S 0 D Y1 S 1 S 0 D Y2 S1 S 0 D Y3 S1 S 0 D
D
AND
Y0 Y1 Y2 Y3
AND
AND AND