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## Chapter 16-3. MOS C-V characteristics

The measured MOS capacitance (called gate capacitance) varies
with the applied gate voltage
A very powerful diagnostic tool for identifying any
deviations from the ideal in both oxide and semiconductor
Routinely monitored during MMOS device fabrication
Measurement of C-V characteristics
Apply any dc bias, and superimpose a small (15 mV) ac
signal
Generally measured at 1 MHz (high frequency) or at variable
frequencies between 1KHz to 1 MHz
The dc bias V
G
is slowly varied to get quasi-continuous C-V
characteristics
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C-V characteristics of MOS-capacitor on p- and n-type Si
C
G

V
G

n-type
The C-V data depends on the measurement frequency as well.
The dotted line represents the low-frequency C-V data.
V
G

C
G

p-type
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Measured C-V characteristics on an n-type Si
N
D
= 9.0 10
14
cm
3

x
ox
= 0.119 m
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MOS-capacitor under accumulation
V
G
< 0
M O S
p-Si
Accumulation of holes
x
Consider p-type Si
under accumulation.

V
G
< 0.
Looks similar to parallel
plate capacitor.

C
G
= C
ox

where C
ox
= (c
ox
A) / x
ox

Thus, for all accumulation conditions, the gate capacitance is equal
the oxide capacitance.
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MOS-capacitor under depletion
Depletion condition:
V
G
> 0
C
G
is C
ox
in series
with C
s
where C
s
can
be defined as
semiconductor
capacitance
C
ox
= c
ox
A / x
ox

C
s
= c
Si
A / W
C
G
= C
ox
C
s
/(C
ox
+ C
S
)
s
A
Si
2
|
c
=
qN
W
where |
s
is surface potential
In this case, the gate capacitance decreases as the gate voltage is
increased. Why?
V
G
> 0
M O S
p-type Si
Depletion of
holes
W Q
M

C
o
x

C
s

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MOS-capacitor under inversion
V
G
>>0
M O S
p-Si
Depletion of
holes
W Q
M

Inversion electrons
o- function
C
o
x

C
s

V
G
= V
T
and V
G
> V
T

Inversion condition |
s
= 2 |
F

2 1
F
A
Si
T
2
2
/
qN
W W
(

|
c
= =
At high frequency, inversion
electrons are not able to respond
to ac voltage. So, to balance the
charge on the metal, the depletion
layer width will vary with the ac.
C
ox
= c
ox
A/x
ox

C
s
= c
Si
A/W
T

C
G
(e ) = C
ox
C
s
/ (C
ox
+ C
S
)
So, C
G
will be constant for V
G
> V
T

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MOS-capacitor under inversion
At low frequency, the inversion electrons will be able to respond to
the ac voltage (Why?). So, the gate capacitance will be equal to the
oxide capacitance (similar to a parallel plate capacitance).

C
G
(e 0) = C
ox
= c
ox
A / x
ox
V
G

C
G

p-type Si
Low frequency
High frequency
C
ox

V
T

C
ox
C
s
/ (C
ox
+C
s
)
For V
G
> V
T
, the high
frequency capacitance
remains constant. Why?
Study exercise 16.4 in text
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Example 1
Consider n-type silicon doped with N
A
=10
16
cm
3
. The oxide thickness
is 100 nm. Plot the C
G
vs. V
G
characteristics when V
G
is varied slowly
from 5 V to +5 V. Assume MOS has area of 1 cm
2
.
Find C
ox
.
Find C
s
(min) when W = W
T
(Note that C
s
decreases as the depletion
layer width increases. It is minimum when the depletion layer width
is maximum, i.e. when W = W
T
).
F 10 47 3 cm 1
cm 10 1000
(As/Vcm) 10 9 8 9 3
8 2
8
14
ox

= .
. .
C
m 298 0 V 357 0 2
cm 10 C 10 6 1
As/(Vm) 10 85 8 9 11 2
2 1
3 16 19
12
T
. .
.
. .
W
/
=
(
(

=

F 10 35 3 cm 1
cm 10 298 0
As/(Vcm) 10
(min)
8 2
4
12
s

= .
.
C
C
G
(min) = (3.47 10
8
3.35) / (3.47+3.35) F = 1.7 10
8
F

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Example 1 (continued)
F s
2 1
s
Si
A
ox
Si
ox s T G
2 when
2
| = |
|
|
.
|

\
|
|
c c
c
+ | = =
/
qN
x V V
= 2.15 V
Plot the C-V characteristics
34.7 nF

V
G

C
G

p-type
2.17 V
17nF

34.7nF

low-f
high-f
Explain why C
G
does not
vary for V
G
> V
T

Question: How will you calculate
C
G
when V
G
= 1V?
s
when V
G
=
1V using the eqn. above. From |
s
find W, then calculate C
s
. Then,
calculate C
G
= (C
ox
C
s
) / (C
ox
+ C
s
)
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MOS-capacitor characteristics: Deep depletion
The previous discussions pertain to the condition when the gate
voltage is ramped slowly, from accumulation condition to depletion
and then to inversion condition. When the ramp rate is high, the
inversion layer does not form and does not have time to equilibrate.
This is called deep depletion condition. In this case, W will
continue to increase beyond W
T
and C
G
will continue to decrease
as shown when the dc bias is varied from accumulation bias to
deep depletion bias.
To calculate W under deep depletion condition, invert the V
G
versus
|
s
relationship. Solve for |
s
1/2
and hence |
s
. Then, calculate W
using W versus |
s
relationship.
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Some observations
V
T
= gate voltage required for start of inversion
= (+) for p-type Si
= () for n-type Si
(
(

|
|
.
|

\
|
|
c c
c
+ | =
2 1
F
Si
A
ox
Si
ox F T
2
2
2
/
qN
x V
(+)
()
(+) - for p-type Si
() - for n-type Si
Higher the doping, higher the |V
T
| value
C
max
= C
ox
and C
min
= C
ox
C
s
/ (C
ox
+ C
s
)
Lower the doping, lower C
s
and hence lower C
min
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Doping dependence of MOS-capacitor high frequency C-
V characteristics, with x
ox
= 0.1 m
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MOS-capacitor under deep depletion
2 1
s
Si
A
ox
Si
ox s G
2
/
qN
x V
|
|
.
|

\
|
|
c c
c
+ | =
2 1
s
A
Si
2
/
qN
W
(

|
c
=
C
s
= c
Si
A / W
C
ox
= c
ox
A / x
ox
C
G
= C
ox
C
s
/ (C
ox
+ C
s
)
n-type Si
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Example 2
Consider example 1. Plot C-V characteristics if V
G
is varied
from 5 V to + 5 V rapidly.
C
G
(5 V) = C
ox
=34.7 nF, as before.
C
G
(V
G
= V
T
) = 17 nF, as before.
s
/
s s
y y . y
.
| = + =
|
|
.
|

\
|
|

+ | =

2 2
2 1
12
16 19
8
where 69 1
10
10 10 6 1 2
3 10 1000 5
Solving for |
s
, we get |
s
= 2.38 V
C
G
(V
G
> V
T
) will continue to reduce (unlike the quasi-steady
state condition of example 1). When V
G
= 5 V,
W = 0.545 m; C
s
= 18.3 nF; C
G
= 12 nF
5V
2.15 V
C
G

V
G

34.7 nF
12 nF
Not under