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Transistors

Transistor Definitions
MOS - Metal Oxide Semiconductor FET - Field Effect Transistor BJT - Bipolar Junction Transistor

MOSFET and BJT


drain collector

body

base

gate

source

emitter npn bipolar transistor

n-channel MOSFET

Basic MOSFET Construction

BJT Symbols
collector collector

base

base

emitter npn bipolar transistor

emitter

pnp bipolar transistor

MOSFET Symbols
drain
gate source or drain body source A. n-channel MOSFET drain

body

gate

body

A circle is sometimes used on the gate terminal to show active low input

source
or drain

gate

gate source

body

B. p-channel MOSFET

Basic MOSFET

Basic CMOS Logic Technology


Based on the fundamental inverter circuit Transistors (two) are enhancement-mode MOSFETs
N-channel with its source grounded P-channel with its source connected to +V

Input: gates connected together Output: drains connected

CMOS Inverter
VDD

A
n

Y = A'

GND

CMOS Inverter - Operation


Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting. When input A is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has a channel enhanced within itself, connecting the output line to the +Vsupply. This pulls the output up to +V (logic 1). When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.

CMOS 2-Input NOR


+V

A
B

Y=A+B

CMOS 2-Input NOR - Operation


This basic CMOS inverter can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. A practical example of a CMOS 2input NOR gate is shown in the figure. In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both Nchannel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output. Note the two p-channel FETs in series.

CMOS 2-Input NAND


+V +V

A
B Y=AB

CMOS 2-Input NAND - Operation


A two-input NAND gate: a logic 0 at either input will force the output to logic 1; both inputs at logic 1 will force the output to go to logic 0. Note the two n-channel FETs in series and the two p-channel FETs in parallel. The pull-up and pull-down resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.

CMOS 2-Input NAND: Buffered


+V
+V

Y=AB

CMOS 2-Input NAND: Buffered


The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either P-channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Typically, the pchannel transistor is approximately twice as wide as the n-channel transistor, because of the difference in conductivity between electronics and holes.

Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here. This is not strictly true for most CMOS devices for applications that are power-switched; special inputs are required for power-off isolation between circuits.

Decoders

Decoder Fundamentals
Route data to one specific output line. Selection of devices, resources Code conversions. Arbitrary switching functions
implements the AND plane

Asserts one-of-many signal; at most one output will be asserted for any input combination

Encoding
Decimal 0 1 2 3 Unencoded 0001 0010 0100 1000
Binary Encoded 00 01 10 11

Note: Finite state machines may be unencoded ("one-hot") or binary encoded. If the all 0's state is used, then one less bit is needed and it is called modified one-hot coding.

Why Encode? A Logarithmic Relationship


8 7 6 5

Log2(N)

4 3 2 1 0 0 25 50 75 100 125 150

2:4 Decoder
A B A B A B
AND 2

EQ3

11 10 01 00

AND 2 A

EQ2

AND 2 A

EQ1

D0 D1

A B

AND 2 B

EQ0

What happens when the inputs goes from 01 to 10?

2:4 Decoder with Enable


A B C A B C A B C
AND 3 A AND 3 A AND 3

EQ3

11 10 01 00

EQ2

EQ1

D0 D1 ENABLE

A B C

AND 3 B

EQ0

Static Hazards

Static Hazard
A
A B Y X1 A B Y

S B

A B

X2

2:1 Mux implemented by minimized Sum-of-Products

Idealized matched delays

Static Hazard
A
A B

In real circuits, delays don't exactly match; Added delay for illustration
AND 2

Y X1

A B

OR 2

S B

BUFF

S DA
B
AND 2 A

Y X2

Static Hazard

We now have a "glitch."

Same waveform, zoomed in.

Static Hazard
AB 00 S=0 S=1 0 0 01 1 0 11 1 1 10 0

Illustrating the minimized function on a Karnaugh map. Only two 2-input AND gates are needed for the product terms

Static Hazard
AB 00 0 0 0 01 1 0 11 1 1 10 0

S
1

The blue oval shows the redundant term used to cover the transition between product terms.

Static Hazard
A
A B
AND 2

Y X1

S B

BUFF

S DA
B A B
AND 2 A

Y X2

A B C

OR 3

AND 2

Y X3

How can we verify the presence and operation of this gate?

Static Hazard
D Q DFC1B CLK CLR A B Y C AND 4 D TCNT

D Q DFC1B CLK CLR

Terminal count of a 4-bit synchronous counter.

D Q DFC1B CLK CLR

CLDCK

D Q DFC1B CLK CLR

ACLR

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Static Hazard
Flight Design Example
D DF1 CLK Q

DF1
CLK VCC Y D0 D1 D2 D3 Y
S1 S0

D DF1 CLK

D DF1 A Y CLK

TMR Triplet

GND

Majority Voter

High-skew buffer

Static Hazard
Flight Design Example

Care is needed when using TMR circuits. First, the output of the voter may be susceptible to a logic hazard glitch. This is not a problem if the TMR is feeding the input of another synchronous input. However, the TMR output should never feed asynchronous inputs such as flip-flop clocks, clears, sets, read/write inputs, etc.
Design Techniques for Radiation-Hardened FPGAs Actel Corporation, September 1997

-- based on SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space Applications and Device Characterization, R. Katz, R. Barto, et. al., IEEE Transactions on Nuclear Science, Dec. 1994.

Static Hazard
We have covered static hazards. There are also dynamic hazards. An example of a dynamic hazard would be when a circuit is supposed to switch as follows:

0 1
But instead switches:

0 1 0 1
Any circuit that is static hazard free is also dynamic hazard free.

Common Output Stage Definitions


VOH - Output voltage when driving high VOL - Output voltage when driving low
IOH - Output current when driving high IOL - Output current when driving low tT - Transition time, usually measured between 10% and 90% of the waveform (2.2)

VOH Test Configuration


VCC

Output Stage

+ i Programmable Load -

VOL Test Configuration


VCC
Output Stage VCC i +

Programmable Load
-

A1460A TID (VOH) Test


Post-Irradiation
0.050 0.040

IOUT(A)

0.030

0.020 S/N LAN3501 S/N LAN3502 S/N LAN3503 S/N LAN3504

0.010

0.000 0 1 2 3 4 5

VOUT

A1460A TID (VOL) Test


Post-Irradiation
0.100

0.080

IOUT(A)

0.060

0.040

0.020

S/N LAN3501 S/N LAN3502 S/N LAN3503 S/N LAN3504

0.000 0 1 2

Vcc-VOUT

RT54SX32 TID (VOH) Test


Post-Irradiation
0.080 0.070 0.060 0.050

IOUT(A)

0.040 0.030 0.020 0.010 0.000 0 1 2 3 S/N LAN4403 S/N LAN4404 S/N LAN4405 S/N LAN4406

VOUT

RT54SX32 TID (VOL) Test


Post-Irradiation
0.080

0.060

IOUT(A)

0.040

0.020

S/N LAN4403 S/N LAN4404 S/N LAN4405 S/N LAN4406

0.000 0 1

Vcc-VOUT

RT54SX16 Rise Time

RT54SX16 Fall Time

Common Interface Levels


TTL 5V CMOS 5V PCI 3.3V PCI LVDS LVTTL

TTL Voltage Specification


VOH - 2.4 V VOL - 0.5 V VIH - 2.0 V VIL - 0.8 V '1' Noise margin = 400 mV '0' Noise margin = 300 mV

5V CMOS Voltages
VOH - ~VDD (no DC load) VOL - ~GND (No DC load) VIH - 70% VDD VIL - 30% VDD '1' Noise margin = ~30% VDD '0' Noise margin =~30% VDD