CHAPTER 5

Computer Arithmetic

Addition and Subtraction of Signed-Magnitude numbers.

Hardware for signed-magnitude addition and subtraction

Bs

B register

AVF

Complementer

M (Mode Control)

Output

Carry
S

Parallel adder

As

A register

Load Sum

Flowchart for add and subtract operations.

Subtract Operation Minuend in A Subtrahend in B Add Operation Augend in A Addend in B

=0
As =

As

Bs
As

=1 Bs

=1
As

As Bs

Bs
As =

=0 Bs

Bs

EA A + B +1 AVF E =0 E =1 AB A =0

EA A + B

AVF E

A<B

A A

A 0

AA+1
AS AS
End (Result is in A and AS)

Hardware for signed 2s complement addition and subtraction

BR Register

Complementer and

V
Overflow

Parallel adder

AC Register

Algorithm for adding and subtracting numbers in signed 2s complement representation

Subtract Add

Minuend in AC
Subtrahend in BR

Augend in AC
Addend in BR

AC

AC+BR + 1

AC

AC+BR

V Overflow

V Overflow

End

End

Numerical Example of Binary Multiplication

Hardware for multiply operation.

Bs

B register

Sequence counter (SC)

Complement and parallel adder

As

Qs

(rightmost bit) Qn

A register

Q register

Flowchart for multiply operation.

Multiply operation

Multiplicand in B
Multiplier in Q

A s Qs Qs Qs

Bs Bs

A0,E0 SC n -1

=0

Qn

=1

EA A + B

Shr EAQ
SC SC - 1

SC

=0 END (product is in AQ)

Hardware for Booths algorithms.

BR register

Sequence counter (SC)

Complement and parallel adder

Qn

Qn + 1

AC register

QR register

Booths algorithm for multiplication of signed-2s complement numbers.

Multiply

Multiplicand in BR Multiplier in QR

AC 0 Qn+1 0 SC n

AC

AC + BR + 1

=10

Qn Q n + 1

=01

AC

AC + BR

=00 =11 ashr (AC & QR) SC SC - 1 0 SC =0

END

2-bit by 2-bit array multiplier.

ao bo

b1

b1 a1 ao b 1 a1 b1 c3 c2 a1 bo c1

bo ao ao bo

a1

b1

bo

co

HA C S C

HA S

c3

c2

c1

co

4-bit by 3-bit array multiplier.

a0 b3 b2 b1 bo

a1 b3 b2 b1 bo

Addend

Augend

4-bit adder
a2 b3 b2 b1 bo Sum and out put carry

Addend 4-bit adder Sum and out put carry c6 c5 c4

Augend

c3

c2

c1

co

Example of binary division

Divisor: B = 10001 01110

11010 0111000000 011100 - 10001 - 010110 - - 10001 - - 001010 - - - 010100 - - - - 10001 - - - - 000110 - - - - - 00110

Quotient = Q Dividend = A 5-bits of A < B, quotient has 5 bits 6-bits of A B Shift right B and subtract; enter 1 in Q 7-bits of remainder B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q; shift right B Remainder B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q Final remainder

Flow chart for divide operation.

Divide operation
Dividend in AQ Divisor in B

Divide magnitudes

Qs SC

As n-1

Bs 0=

Sh1 EAQ E =1 A A+B+1

A B

EA A+B+1 EA A + B + 1 =1
A B

=0
A < B

E
A < B

=1 =0

EA A+B DVF 1

EA A+B DVF

EA A + B SC
=0

Qn 1

SC - 1 SC
0

END Divide overflow

END Quotient is in Q Remainder in A