Digital Electronics: Arslan Qamar Malik Lecturer

Arslan Qamar Malik Lecturer
DIGITAL ELECTRONICS
CHAPTER 1
Basic Logic Operations

There are 5 basic logic operations representing the digital electronic circuits.
NOT
AND
OR NAND
NOR
Digital Logic Circuits Gates

The device/circuit that performs single logic operation is called Gate.
Combinational Gates
The gates that perform one or more of the basic
logical operations are referred to as Combinational Gates. Outputs depend only on the present value of the inputs.
Digital Logic Circuits Gates

Sequential Gates
The gates that perform sequential logic
operations are referred to as Sequential Gates. Outputs depend on the past values of the inputs as well as present values.
Digital Logic Circuits States

For all digital circuits, a variable can only have two states, 0 and 1. Such variable is called Binary variable. Considering voltage as a variable, Binary 0 state representing low voltage and binary 1 state representing high voltage.
Digital Logic Circuits Inverter

If the input voltage is low, the output voltage will be high and vice versa.
Since this device performs logical NOT
operation, this device is also called NOT gate.
It makes no difference if the inverting circle is
at the input or output.
Digital Logic Circuits NonInverter

Non-Inverting devices are also termed as Buffers.
Buffers are used to regenerate voltage levels.
Buffers adjust degraded high levels to higher and degraded low levels to lower.
Ideal Logic Inverter

A typical operating voltage of
many logic families is 5V. Ideal Power dissipation of all logic families is zero. In actual case, the power dissipation is minimized for optimum design.
Ideally, the logical 1 output voltage is at the power supply voltage Vcc. Ideally, the logical 0 output voltage is at ground (0V).
Ideal Logic Static & Power Characteristic

Ideally, the transition between output logic
states occurs abruptly at an input of Vcc/2. Logical input 0 is represented by the voltage range 0 VIN < Vcc/2. Logical input 1 is represented by the voltage range Vcc/2 < VIN < Vcc. VIN = Vcc/2 has an undefined output and gives unpredictable results.
Ideal Logic Transient Characteristic

Upon transition of the input from logical 0 to
logical 1, the output instantaneously switches from logical 1 to logical 0 without any delay. In actual case, the transition between states is not instantaneous and a delay between the output and input transitions is present.
Ideal Logic Input & Output Impedances

Transient response and driving ability (fan-out)
of logic gates are directly dependent upon the gates input and output impedance.

The previous figure shows a logic inverter driving
multiple (identical) logic inverters. It is observed that the driving gate must provide enough output current to drive all the load gates. IOUT = NIIN where the primed terms referred to load gates. The input current is zero for a very large input impedance and driving capabilities are maximized. An infinite input impedance is desired to obtain infinite driving capability.

The input capacitance of load gates must be
charged through the output resistance of the driving inverter. Thus, a smaller output resistance will provide a larger charging current for the load capacitance and a faster switching time. Ideally, the output resistance must be zero. A smaller input capacitance can also speed up the switching time of the load gates.
Inverter Voltage Transfer Characteristic

Voltage Transfer Characteristic (VTC) for logic
inverters have been standardized. VTC is the graph between Vout and VIN. On vertical axis, VOH and VOL correspond to output high and output low voltage levels respectively. On the horizontal axis, VIL is input low voltage and VIH is the input high voltage.

As the input voltage is increased from 0V, VIL is
the maximum input voltage that provides a high output voltage (logical 1 output). VIH is the minimum input voltage that provides a low output voltage (logical 0 output). VOH, VOL, VIL and VIH are referred to as the critical voltages of the VTC.

VOH > VIH
VOL < VIL

Midpoint Voltage:
Sometimes referred as Threshold voltage (Vth). The voltage at which Vout = VIN on VTC is referred as
Midpoint voltage. Midpoint voltage can be found graphically by superimposing (the unity slope) Vout = VIN and finding its intersection with the VTC.
Logic Swing and Transition Width

Logic Swing
The magnitude of voltage difference between the
output high and low voltage levels. VLS = VOH VOL
Transition Width
The amount of voltage change that is required of the
input voltage to cause a change in the output voltage from the high to the low level (and vice versa). VTW = VIH - VIL
Noise in Digital Circuits

Noise
Variations in the steady-state voltage levels of digital
circuits (i.e. Logical 1 and logical 0 states) are undesirable and cause logic errors. This variation is termed as Noise.
Noise Margins
Voltage Noise Margin represents the safety margin
for the high and low voltage levels. Noise voltages must have magnitudes less than the voltage noise margins. VNMH = VOH VIH VNML = VIL - VOL

Noise Sensitivities
The effects of input variations are quantified in terms
of the noise sensitivities. The high noise sensitivity is defined as the difference between input and midpoint voltage for VIN at VOH. The low noise sensitivity is defined as the difference between input and midpoint voltage for VIN at VOL. VNSH = VOH VM VNSL = VM - VOL

Noise Immunities
The ability of a gate to reject noise.
The high and low noise immunities are defined as the
quotient of the noise sensitivities and the logic swing. VNIH = VNSH / VLS VNIL = VNSL / VLS

FAN-IN and FAN-OUT
A general logic gate has multiple inputs and multiple
outputs. By multiple outputs we mean the output of a given gate is connected to (driving) the inputs of several load gates. FAN-IN: the number of inputs of a gate. FAN-OUT: the number of outputs of a gate. Maximum FAN-OUT depends on the input and output current of a driving gate. The maximum fan-out possible during the driving gates logical 1 output state is Nhigh = IOUT (high)/ IIN (high)

FAN-IN and FAN-OUT
The maximum fan-out possible during the driving
gates logical 0 output state is Nlow = IOUT (low)/ IIN (low)
Transient Characteristics
Switching Speed Definitions
td = delay time
tr = rise time
ts = storage time tf = fall time
ton = turn on time

toff = turn off time
ton = td + tr toff = ts + tf
Propagation Delays
When the input voltage changes from one level to
another, the output voltage response is delayed in time. This is referred to as Propagation Delay.
The low to high propagation delay time tPLH refers
to the low to high transition of the output. The high to low propagation delay time tPHL refers to the high to low transition of the output. The overall propagation delay time tp(avg) is tp(avg) = (tPLH + tPHL) / 2
Power Dissipation
Power Dissipation for an ideal gate is obtained by
realizing that it is equal to the power supplied. This is true for a gate with single power supply. Power dissipation is different for the output high (logical 1 output) and output low (logical 0 output) states and they are termed as PCC(OH) and PCC(OL), respectively. The average power dissipation for a gate with the two possible output states as follows: PCC(avg) = (PCC(OH) + PCC(OL) )/ 2
Power Dissipation
PCC(avg) = [ (ICC(OH) + ICC(OL) ) / 2 ] x VCC
Some logic circuits have 2 power supplies, one with a positive voltage and one with a negative voltage. In this case, both currents (ICC and IEE) are obtained for
each of the output high and output low logic states.
Power Dissipation
Average power supplied by the gate with two possible states is then as follows:
Power Delay Product

Low power dissipation and short propagation delay times are both desirable for digital logic circuits.
Faster propagation delay times are achieved at the cost of increased power dissipation.
Lower power dissipation results in longer propagation
delays. Power Delay Product is the merit for digital logic gate and is represented as follows: PD = PDISS(avg) x tp(avg) Smaller the Power Delay Product is for a gate, the more ideal the gate is. Ideally, PD equals to 0 Joules.
METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

CHAPTER 16
Introduction to MOSFET
BJTs are current-controlled devices. The
current controlling terminal is Base. FETs are voltage-controlled devices. The current controlling terminal is Gate. In FETs, the current-controlled mechanism is based on an electric field established by the voltage applied to the Gate. BJTs are Bipolar Junction transistors i.e. The current is due to the movement of both types of charge carriers e.g. Holes and Electrons.
Introduction to MOSFET
FETs are uni-polar devices i.e. The current is
due to the movement of the only one of the two types of charge carriers e.g. either due to Holes or due to Electrons. Metal-Oxide Semiconductor FET (MOSFET) is a very popular kind of FET due to the following.
MOS transistors can be made quiet small. Manufacturing process is comparatively simple.
Digital Logic operations can be implemented
using only MOSFETs.
N-MOSFET
Metal Gate N-MOSFET
The Enhancement-Type N-MOSFET is the most widely
used FET. The transistor is fabricated on p-type substrate. Two heavily doped ntype regions are created in p-type substrate. A thin layer of SiO2 (a perfect insulator) is on the surface of the substrate which ensures IG=0A.
N-MOSFET
Metal is deposited on top of the oxide layer to form
the Gate electrode of the device. Other terminals i.e. Source, Drain and substrate are also made over metal surface.
That is how the name of
the device is set as Metal Oxide Semiconductor FET.
N-MOSFET
Silicon Gate N-MOSFET
Most of the modern MOSFETs are fabricated using a
process known as Silicon-Gate Technology. Gate electrode is formed using a certain type of silicon named Polysilicon.
Enhancement-type N-MOSFET
Operation with No Gate Voltage
Two back to back diodes exist in series between drain
and source. One diode is formed by pn-junction between n+ drain and p-type substrate. Second diode is formed by pn-junction between n+ source and p-type substrate. These diodes prevent current conduction from drain to source when voltage VDS is applied. Both pn-junctions must be made Reverse-Biased.
Creating a Channel for Current Flow
Lets have VDS = 0V (source and drain are grounded). Applying VGS (gate to source voltage) at Gate making
free holes being repelled and pushed downwards in the p-type substrate.
The Depletion
region is now populated by the electrons under the Gate region.
When a significant number of electrons accumulate
under the Gate, an n-region is created that connects Drain and Source regions. Applying VDS, current flows through this induced nregion. This induced region will now become a Channel for current to flow from Drain region to source region. The device is now named as N-channel MOSFET. Note that the N-channel is created in p-type substrate.
Device Symbol
N-channel enhancement-type MOSFET
N-MOSFET Modes of Operation

Threshold Voltage
The value of VGS at which a significant number of
mobile electrons accumulate in the channel region to form a conducting channel is called Threshold Voltage. It is denoted by Vt. For n-channel MOSFET, Vt is positive. To conduct current from Drain to Source terminal, the VGS must be greater than Vt. Greater the VGS from Vt, wider will be the channel and greater will be the flow of current (if VDS >0). Effective Voltage = VGS - Vt.

Increasing VGS above the threshold voltage (Vt)
enhances the channel, hence the device named as Enhancement-type N-MOSFET. Gate current is negligibly small thus current entering at the drain terminal is equal to the current leaving at the source terminal.

Cutoff Mode If VGS for N-MOSFET is less than Vt, the device is
in the cutoff mode of operation and no current flows in the channel.
Linear Mode
As VGS is increased above Vt, the device is in Linear
mode and ID is proportional to that increase.

ID is also proportional to the increase in VDS that causes ID to flow. VDS should be less than (VGS- Vt). ID (Linear) = k[(VGS- Vt) VDS (V2DS/2)] k is the transconductance parameter.

Saturation Mode If VDS is increased above the effective voltage
(VGS- Vt) while VGS > Vt, the device operates in the Saturation mode. It is evident that the VDS is dropped successfully along the length of the channel and the less amount will be available at the Source end if compared it with the value at Drain end.

Saturation Mode
Thus for a constant value of VGS (i.e. VGS> Vt), ID is no longer in direct proportion of VDS and the
current starts levelling off and maintains level for further increase in VDS. This condition is called Pinched-off.
ID (Sat) = k[(VGS- Vt)2]/2 ID (Sat) = k[(VGS- Vt)2(1+ VDS)]/2 Where is channel-length modulation parameter

Saturation Mode
At pinched-off, the depth of the channel is
decreased to zero but the flow of current is not cut-off rather it is maintained from Drain to Source. Pinched-off occurs at VDS = VGS - Vt
Family of Curves
The ID versus VDS graph is plotted to identify
the family of curves. Three modes of operation are evident in the graph.
MOSFET: Device & Process Transconductance Parameters

The parameter k is referred to as Device Transconductance parameter of a MOSFET.
W and L are channels width and length respectively. The parameter k is referred to as Process Transconductance parameter and its value is set at the fabrication level.

The parameter k is calculated by the following
expression:
is the electron/hole mobility in the channel. COX is the gate oxide capacitance per unit area.
Different electron mobility is set industrially for N-channel and P-channel MOSFET. Electron mobility is related to the average drift of electrons/holes under the influence of electric field.

N-channel MOSFET, the electron mobility is
N = 580 cm2/V.s
P-channel MOSFET, the hole mobility is
N = 230 cm2/V.s
MOSFET: Gate Capacitance per Unit Area (COX)

COX is the Gate capacitance per unit area of
the parallel-plate capacitor formed by the Gate electrode and the Channel.

Dielectric is provided by the silicon oxide layer between Gate electrode and Channel.
COX = OX / tOX OX is the permittivity of the silicon oxide which is the measure of the ability of Silicon oxide to be polarized by the electric field. tOX is the thickness of the oxide layer.

OX = 3.9 x O
O is the permittivity of vacuum.
O = 8.854 x 10-12 F/m
thus
OX = 3.45 x 10-11 F/m
P-MOSFET
The P-channel MOSFET is fabricated on n-type
substrate.
Two heavily doped p-
type regions are created in n-type substrate. In P-MOSFET, the free charges which move from end-to-end are positively charged (holes).
P-MOSFET
The device operates in exactly the similar manner as N-MOSFET.
VGS and VDS are negative voltages.
Thus, Vt is a negative Threshold voltage.

The current ID enters the Source terminal and leaves through the Drain terminal.
P-MOSFET
Cutoff Mode
VSG - Vt ID = 0A
Linear Mode
VSG - Vt VSD VSG + Vt ID (Linear) = k[(VSG+ Vt) VSD (V2SD/2)]
Saturation Mode
VSG - Vt VSD VSG + Vt ID (Sat) = k(VSG+ Vt)2/2, ID (Sat) = k[(VSG+ Vt)2(1+ VSD)]/2
Gate Oxide Capacitances

CGD is the capacitance between Gate and Drain.
CGS is the capacitance between Gate and
Source. CGB is the capacitance between Gate and Body.
Gate Oxide Capacitances

Total Gate Capacitance is the sum of the capacitances between Gate and remaining regions of semiconductor.
CG = CGS + CGD + CGB CG = L*W* COX
Junction Capacitances
CDB is the capacitance between Drain and
Body. CSB is the capacitance between Source and Body.
Exercise
Consider a process technology for which Lmin=0.4m, tox =8nm, N = 450cm2/V.s
Vt = 0.7V
a) Find Cox and kn
b) For MOSFET with Width=8m and Length=0.8m,
calculate the values of VGS and VDS(min) needed to operate the transistor in the saturation mode with a dc current (ID ) equals 100A. c) Find the value of VGS required to cause the device to operate as a 1k resistor for a very small VDS.
Depletion-Type N-MOSFET
The Depletion-Type MOSFET has a physically implanted channel.
The n-channel depletion-type MOSFET has a
n-type silicon region (channel) connecting the n+ source and n+ drain regions. The channel exists above the p-type substrate. Since the channel is present, current flows by applying VDS, when VGS = 0V
Same as in enhancement-type MOSFET, the channel depth and conduction is controlled by applying VGS. Applying positive VGS enhances the channel.
Applying negative VGS reduces the channel
depth and decreases conductivity. The mode of operation (negative VGS) is called Depletion Mode. Thus the type Depletion-Type MOSFET.
Threshold Voltage
As VGS is getting more negative, a value will reach
when the channel is completely depleted of all charge carriers (ID = 0A). The current remains zero for further increase in VDS. This negative value of VGS is the Threshold Voltage. The device will not work if VGS is less than the threshold voltage.
The ID-VDS characteristics of a depletion-type
n-channel MOSFET is shown below.
The vertical line shows the channel is solid. When the body is connected with the source,
the right symbol will be used. The shaded area is represented the implanted channel.
The ID-VGS characteristic of a depletion-type
n-channel MOSFET is shown below when the device is in saturation mode. IDSS is the drain current when the device is in saturation mode and VGS = 0V.
Depletion-Type P-MOSFET
In P-MOSFET, the polarities of all voltages
(including Vt) are reversed. In P-MOSFET, the ID flows from the source terminal and leaves at the drain terminal.
The graph shows
the behaviour of two types of MOSFETs when they are operating in saturation mode.
Exercise
For a Depletion-Type NMOS Transistor with Vt= -2V, and k = 2mA/V2, find the minimum VDS required to operate in the saturation
region when VGS = +1V. What is the corresponding value of ID?
Exercise
The Depletion-Type MOSFET has k = 4mA/V2 and Vt= -2V. Neglecting the effect of VDS on ID in the saturation region, find the voltage that
will appear at the source terminal.
MOSFET circuits at DC
Design the circuit so that the transistor
operates at ID = 0.4mA and VD = +1V. The NMOS transistor has Vt =2V, nCOX = 20A/V2, L = 10m and W = 400m. Neglect the channel modulation effect (=0).
Design the circuit to obtain ID = 0.4mA. Find
the value required for R and the dc voltage VD. The NMOS transistor has Vt =2V, nCOX = 20A/V2, L = 10m and W = 100m. Neglect the channel modulation effect (=0).
Design the circuit to establish drain voltage of
0.1V. What is the effective resistance between drain and source at this operating point? Let Vt =1V, kn(W/L) = 1mA/V2.
Analyse the circuit to determine the voltages
at all nodes and the currents through all branches. Let Vt =1V, kn(W/L) = 1mA/V2. Neglect the channel length modulation effect (=0)..
RESISTOR LOADED NMOS INVERTER (CHAPTER 18)
MOSFET Amplifier & Switch

MOSFET acts as Voltage-controlled current
source as long as the device is in Saturation region. Linear Amplification is achieved by following the two steps:
DC bias the MOSFET device Superimposing the input signal to be amplified on
the dc bias voltage.
For the linear amplification, the input voltage
(Vi) is kept small to make the change in drain current proportional to the change in Vi.
Large Scale Operation

Graphical Representation of Voltage Transfer
Characteristics
Large Scale Operation

Transfer Curve
Superimpose the
input voltage Vi on the dc bias voltage.
Operation as a Switch
To use MOSFET as a switch, the device is to operate at the extreme positions in the transfer curve. The device is turned off when Vi < Vt. This is the extreme left position on the transfer curve i.e. Vo = VDD and ID = 0A. The device is turned on when Vi = VDD. This is the extreme right position on the transfer curve i.e. Vo = 0V and ID is maximum.
Operation as a Switch
The MOSFET is behaving as a Logic Inverter. High voltage level is close to VDD and Low voltage level is close to 0V.
Operation as a Linear Amplifier

To operate MOSFET as a Linear Amplifier, we
make use of the saturation region of the transfer curve. The device is biased at a point in the middle of the transfer curve. The biased point is called Quiescent Point and is denoted by Q. The voltage signal to be amplified is then superimposed on dc bias voltage VIQ.

VI should be taken small to restrict the
operation in almost linear segment of the transfer curve. The output voltage Vo will be then proportional to the input voltage Vi. The Linear Amplifier produces the same waveform with the larger factor defined by the voltage gain of the amplifier. Since the slope is negative, the CS-amplifier is an inverting Amplifier.

If the amplitude of the input signal VI is
increased, the output signal will become distorted since the operation will no longer be restricted to the saturation region of transfer curve.

Care must be made in deciding the position
of the Q-point on the transfer curve.

VOQ should be lower than VDD by sufficient amount and higher than VOB by sufficient
amount to allow the required positive and negative output swing.
Analytical Expressions of Transfer Characteristics

Cut-off Region
Vi < Vt Vo= VDD
Saturation Region
Vi > Vt Vo > Vi Vt ID (Sat) = k(Vi - Vt)2/2 By putting the value of ID(sat) in the dc bias equation (VO =
VDD - IDRD), VO can be calculated.

Triode Region
Vi > Vt Vo < Vi Vt
ID (Triode) = k[(Vi- Vt) VO (V2O/2)] OR

ID (Triode) = k[(Vi- Vt) VO], as VO is small in Triode region. By putting the value of ID(triode) in the dc bias equation (VO
= VDD - IDRD), VO can be calculated.
The drain-to-source resistance near the origin of the iD-vDS
plane can be calculated as

Voltage Gain (Saturation Region)
The voltage gain at the bias point Q at which the
Vi = ViQ is as follows.
Utilize the above equation, the voltage gain is

Voltage Gain (Saturation Region)
Another way of finding voltage gain is as follows.
Vi = ViQ
Vo
= VOQ - Vt
Overdrive voltage = VOV = Vi
Utilize the above equations, the voltage gain is

Remaining critical points of VTC can be calculated as follows: Input Low Voltage (VIL)
Input High Voltage (VIH) Midpoint Voltage (VM)
Exercise
Consider the following CS circuit. Construct the Voltage Transfer Characteristic for the case when kn(W/L) = 1mA/V2, Vt = 1V, RD =
18k and VDD = 10V.
Exercise (contd.)
In the picture on left, the input signal (Vi) of 150mV peak-to-peak amplitude is applied. The picture on right shows the VTC with superimposed input signal.
SATURATED ENHANCEMENT-ONLY LOADED NMOS INVERTER
Saturated Enhancement-Only Loaded NMOS Inverter

In the previous section, we have discussed Resistor Loaded NMOS Inverter. In this section, the behaviour of an Inverter with
two Enhancement-Only NMOS transistors will be studied. This type of inverter is more practical than resistor-loaded inverter since the resistor is thousands of times larger than a MOSFET. Remember, any logic operation can be implemented using just MOSFET devices.
Operation: Saturated EnhancementOnly Loaded NMOS Inverter

The figure shows that the inverter is connected with a Saturated Enhancement-Only NMOS transistor as a Load device. With the Gate and Drain of the load NL connected,
VDS,L = VGS,L > VGS,L - VT,L
Thus the load device can only operate in Saturation mode.

The input to the inverter is at Gate terminal of the output transistor (NO).
VIN = VGS,O
VOUT = VDS,O = VDD - VDS,L
The NO is in cut-off region when VIN < VT,O. The NL is still in saturation region.
VOUT = VDD - VGS,L

Since NO is in cut-off region, ID,L = 0A.
ID,L = kL (VGS,L VT,L)2 / 2 = 0 VGS,L = VT,L
VOUT = VDD - VT,L
Thus the output is VDD degraded by the value of threshold voltage of NL.

When VIN > VT,O, the transistors NO and NL begin to conduct equal drain currents. As VDS,O VGS,O VT,O, NO is in Saturation mode.
ID,O (Sat) = ID,L (Sat) kO (VGS,O VT,O)2 / 2 = kL (VGS,L VT,L)2 / 2
Since VGS,O = VIN and VGS,L = VDD - VOUT

kO (VIN VT,O)2 / 2 = kL (VDD - VOUT VT,L)2 / 2
Solving the equation for VOUT, we have

When VDS,O VGS,O VT,O , NO transistor is in Triode region of operation. NL transistor is still in saturation region of
operation.

Graphical Representation of Voltage Transfer Characteristics
ID,O = ID,L
VDS,L = VDD - VDS,O

ID,L = kL [(VDD VT,L) VDS,O]2 / 2
The above equation works in
similar manner as the load line equation for the resistorloaded transistor.

The voltage transfer characteristic can be obtained in the same graphical manner as the resistorloaded NMOS inverter.
Unlike the resistor-loaded inverter, the curve for load transistor (NL) is non-linear.
VGS,O and VDS,O are read from the intersection of
output load curve with the family of curves. These points are then mapped into the VGS,O and VDS,O coordinate axes.

The resulting curve is the transfer curve. In this transistor, VIL is defined as the threshold voltage of NO.

Analytical Expressions of VTC
Cut-off Region
VIN = VGS,O VGS,O < VT,O
VOH = VDD - VT,L In resistor-loaded transistor, VOH = VDD.
Saturation Region
VGS,O > VT,O VDS,O VGS,O VT,O

Triode Region
NL is in saturation region and NO is in Linear or Triode
region of operation.
Operation: Saturated EnhancementOnly Loaded NMOS Inverter Analytical Expressions of VTC

Remaining critical points of VTC can be
calculated as follows:
Input Low Voltage (VIL) Input High Voltage (VIH) Midpoint Voltage (VM)
LINEAR ENHANCEMENT-ONLY LOADED NMOS INVERTER
Linear Enhancement-Only Loaded NMOS Inverter

In the previous section, we have discussed
Saturated-Loaded NMOS Inverter. In this section, the behaviour of Linear Enhancement-Only loaded NMOS inverter will be studied. The advantage of using this type of inverter is that the output will be equal to the supplied source voltage rather than degraded by the value of VT,L.
Linear Enhancement-Only Loaded NMOS Inverter

The disadvantage of using this type of
inverter is the use of two separate DC supplies. Hence the type is less practical than the Saturated-loaded NMOS inverter. Again, any logic operation can be implemented using just MOSFET devices.
Operation: Linear EnhancementOnly Loaded NMOS Inverter

The figure shows that the inverter is
connected with a Linear EnhancementOnly NMOS transistor as a Load device.

The Load can operate in the Linear region by applying a separate, larger voltage
source to the gate of NL. The Gate voltage should satisfy:

VGG > VDD + VT,L

VIN = VGS,O
VOUT = VDS,O = VDD - VDS,L

VOUT = VGG - VGS,L
The NO is in cut-off region when VIN < VT,O. The NL is still in Linear region.
VOUT = VDD - VDS,L

ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2] = 0 After solving the above equation, VDS,L = 0V
VOUT = VDD - VDS,L = VDD
In the case of Saturated Enhancement-only

load, the output was degraded by the value of threshold voltage of NL. In this case, the maximum output is achieved when NO is cut-off.

ID,O (Sat) = ID,L (Linear) kO (VGS,O VT,O)2 / 2 = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2]
Apply the following substitutions:

VGS,O = VIN VGS,L = VGG - VOUT VDS,L = VDD - VOUT

When VDS,O VGS,O VT,O , NO transistor is in Triode region of operation. NL transistor is also in Linear region of operation.

ID,O = ID,L VDS,L = VDD - VDS,O VGS,L = VGG - VDS,O
ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2] ID,L = kL [(VGG - VDS,O VT,L) (VDD - VDS,O) 2] - (VDD - VDS,O) 2 / 2]
The above equation works in
similar manner as the load line equation for the resistorloaded transistor and Saturated NMOSFET loaded transistor.

The voltage transfer characteristic can be obtained in the same graphical manner. The curve for load transistor (NL) is non-linear.
VGS,O and VDS,O are read from the intersection of output load curve with the family of curves. These points are then mapped into the VGS,O and VDS,O coordinate axes.

The resulting curve is the transfer curve.
The output does not reach 0V as the input increased to the maximum value of supply voltage.
This can be confirmed
while looking at the family curve of this type of transistor (i.e. VIN = VDD).

Cut-off Region
VIN = VGS,O
VGS,O < VT,O VOH = VDD In resistor-loaded transistor, VOH = VDD. In Saturated-loaded NMOS, VOH = VDD - VT,L.

Saturation Region
VGS,O > VT,O VDS,O VGS,O VT,O VIN = VGS,O VDS,L = VDD - VOUT VGS,L = VGG - VOUT

Triode Region
NL and NO are in Linear or Triode region of operation.
Operation: Linear EnhancementOnly Loaded NMOS Inverter Analytical Expressions of VTC

Input Low Voltage (VIL)
Input High Voltage (VIH)
Operation: Linear EnhancementOnly Loaded NMOS Inverter Analytical Expressions of VTC

Midpoint Voltage (VM)
ENHANCEMENT-DEPLETION LOADED NMOS INVERTER
Enhancement-Depletion Loaded NMOS Inverter

In the previous section, we have discussed
Linear Enhancement-only NMOS Inverter. In this section, the behaviour of Linear Enhancement-Depletion loaded NMOS inverter will be studied. The advantage of using this type of inverter is that the output will be equal to the supplied source voltage without the second VGG.

More abrupt VTC transition is noticed for
this kind of MOSFET. This type of inverter is more widely used in NMOS digital logic circuits. Again, any logic operation can be implemented using just MOSFET devices.

The figure shows that the inverter is
connected with a Enhancement-Depletion NMOS transistor as a Load device.

The Load can operate in the Linear and saturation region of operation.
With the Gate and Source connected together,

VGS,L = 0V.
Operation: EnhancementDepletion Loaded NMOS Inverter

Since the threshold voltage of this load is
negative, we have
VGS,L = 0 > VT,L
Thus the load is always active. The region of operation for NL is found by
the equation:
VDS,L > VGS,L- VT,L = - VT,L = | VT,L |

VIN = VGS,O VOUT = VDS,O = VDD - VDS,L
The NO is in cut-off region when VIN < VT,O. The NL
is in Linear region of operation.

ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2] = 0 After solving the above equation, VDS,L = 0V VOUT = VDD - VDS,L = VDD

ID,O (Sat) = ID,L (Linear) kO (VGS,O VT,O)2 / 2 = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2]
Apply the following substitutions:

VGS,O = VIN VGS,L = 0V VDS,L = VDD - VOUT

When the output drops below VDD VT,L , VDS,L becomes large enough for NL to enter the saturation region.
ID,O (Sat) = ID,L (Sat) kO (VGS,O VT,O)2 / 2 = kL [(VGS,L VT,L) 2 (1 + LVDS,L ) / 2
Since ID,L is less dependent on VDS,L , thus the drain current will be constant with respect to the output (VDS,O).
When VDS,O VGS,O VT,O , NO transistor is in Triode region of operation.

ID,O = ID,L VDS,L = VDD - VDS,O VDS,L = VDD VOUT
When Load is in Linear:
ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2] ID,L = -kL [ VT,L (VDD - VDS,O) 2] - (VDD - VDS,O) 2 / 2]
When Load is in Saturation:

ID,L = kL [(VGS,L VT,L) 2 (1 + LVDS,L ) / 2

The voltage transfer characteristic can be obtained in the same graphical manner. The curve for load transistor (NL) is non-linear.
VGS,O and VDS,O are read from the intersection of output load curve with the family of curves. These points are then mapped into the VGS,O and VDS,O coordinate axes.

The resulting curve is the transfer curve. The output does not reach 0V as the input increased to the maximum value of supply voltage.
This can be confirmed
while looking at the family curve of this type of transistor (i.e. VIN = VDD).
Operation: Enhancement-Depletion
Loaded NMOS Inverter
Cut-off Region
VIN = VGS,O
VGS,O < VT,O VOH = VDD In resistor-loaded transistor, VOH = VDD. In Saturated-loaded NMOS, VOH = VDD - VT,L. In Linear-loaded NMOS, VOH = VDD.
Saturation Region
VGS,O > VT,O VDS,O VGS,O VT,O VIN = VGS,O VDS,L = VDD - VOUT VGS,L = 0V
Triode Region
NL and NO are in Saturation and Linear region of
operation respectively.
Loaded NMOS Inverter Analytical Expressions of VTC
Loaded NMOS Inverter Analytical Expressions of VTC
Midpoint Voltage (VM)
NMOS GATES
NMOS Gates
In this chapter, we describe the design of
multi-input NMOS logic gates such as NAND, NOR, complex AND-OR-Inverts (AOI) and other special function logic gates. Each of these gates has a single Load device in the same fashion as the NMOS inverters.
NMOS NOR Gate

The NMOS inverter with a resistor or MOSFET connected as a load device can be made to perform the logical NOR function. This can be done by placing the additional NMOS transistors in parallel with the output NMOS transistor.
NMOS NOR Gate

Each of the output N-channel MOSFET should have the same channel width (W) and length (L) to achieve the same value of VOL regardless of which input is high. We have discussed that Enhancement-Depletion NMOS inverter is more practical inverter than any other kind.
NMOS NOR Gate

Output High Voltage If both inputs of NMOS NOR gate are low, both output transistors (NA and NB) will be cutoff. The output will be unchanged from that of inverters discussed in previous sections. For Enhancement-Depletion loaded NMOS inverter, VOH = VDD. For Saturated-Enhancement, VOH = VDD VT,L For Resistor /Linear Enhancement VOH = VDD
NMOS NOR Gate

Output Low Voltage If any of the inputs is high, a highly conductive path from the output to ground is formed by enhancement of a drain-to-source channel. Thus low voltage will be achieved at the output. Thus, logical NOR operation is achived. This parallel output NMOS structure is referred to as a Parallel Pull-down as there are several pull down paths from the output to ground.
NMOS NOR Gate

How VOL can be improved?
The output low voltage is inversely dependent
upon ko. Single Input Voltage High

If single input voltage is high, the VOL will be same as of single input inverter.
NMOS NOR Gate

Both Input Voltages high If both inputs are high, both transistors will conduct drain current. If both input voltages are same and process transconductance parameter is same, the output transistor can be considered to act as a single Nchannel MOSFET. The device transconductance parameter (k0) will be:
NMOS NOR Gate

Since the VOL is inversely proportional to kO, the VOL will be reduced for an NMOS NOR gate with two inputs high. More inputs can be added by adding more parallel output NMOS transistors. In this way, the VOL can be improved (i.e. more close to 0V) by making multiple inputs high. VOH is not dependent on increasing number of inputs.
NMOS NOR Gate

The input low voltage of NOR gates is same as
those for the corresponding single inverter.

The input high voltage of NOR gates is same as
those for the corresponding single inverter.
NMOS NAND Gate

The NMOS inverter with a resistor or MOSFET connected as a load device can be made to perform the logical NAND function. This can be done by placing the additional NMOS transistors in series with the output NMOS transistor. The gate terminal of each
NMOS transistor is used as a NAND logic gate input.
NMOS NAND Gate

Each of the input N-channel MOSFET
should have the same channel width (W) and length (L). We have discussed that EnhancementDepletion NMOS inverter is more practical inverter than any other kind.
NMOS NAND Gate

Output High Voltage VA Low, NA cutoff
If bottom transistor NA has low input gate voltage, then NA will be in cutoff state and the source terminal of NB has no conductive path to ground. Thus regardless of the input state for NB, the NAND gate must be in the output high state.
VB Low, NB cutoff We consider VA in the input high state, NA will be active and a conductive path exists from source of NB to ground. Thus source of NB is at virtual ground since VDS,A is very small due to zero ID,A.
NMOS NAND Gate

NB is now acting like an inverter. Low input voltage makes NB in cutoff state and no pull-down path exists from the output to the virtual ground. Thus, the high output state is noticed at the output. Thus, either input low results in output high state and the NAND functionality will be achieved. The output high voltage will be unchanged from other NMOS inverters. VB Low, VA Low
Both inputs low yields the output high state verifying the logical NAND operation.
NMOS NAND Gate

Output Low Voltage For VA = VGS,A is high, the NA will be active and a conductive path exists from source of NB to ground. Thus source of NB is at virtual ground. For VB is high, the NB is also active and a conductive path exists from the output to the virtual ground. Thus the NAND gate is in the output low state due to the pull-down path available from output to virtual ground.
NMOS NAND Gate

The VOL is degraded (increased) from the single
inverter by following the stacked pull-down configuration of NMOS transistors. There will be a longer pull-down path from the output to ground. That means the length of the two channels will be added. If width and process transconductance parameters remain constant, then
NMOS NAND Gate

Since VOL is inversely proportional to device
transconductance parameter (ko), low value of ko will increase the VOL. A greater channel width is needed for each transistor to compensate this degradation of VOL. Due to this degradation of performance, the NMOS NOR gates are preferred over NMOS NAND gates. NMOS NAND gates can accommodate more than two inputs (ideally up to 3) by simply adding more NMOS transistors in series to the pull-down sequenced transistors.
NMOS NAND Gate

The input low voltage of NAND gates is dependent
on ko.

The input high voltage of NAND gates is dependent
on ko.
NMOS OR/AND Gate

OR Gate: can be obtained using NMOS logic families by simply connecting inverter to the output of NOR gate.
NMOS OR/AND Gate

AND Gate: can be obtained using NMOS logic families by simply connecting inverter to the output of NAND gate.
NMOS Complex Logic Gates

Complex AND-OR invert logic gates can be constructed by connecting NMOS transistors in series and parallel combinations within the
same circuit. Class Work: Design the Enhancement-depletion loaded

NMOS logic gates for the following logic functions.
F = (AB + CD) F = AB + CD F = ABC + D + EF F = ((A+B)(C+D) + E(F+G))

Following is the design of NMOS logic gate performing logic function: (AB + CD)

Following is the design of NMOS logic gate performing logic function:
((A+B)(C+D) + E(F+G))

Determine the logic function for the following circuit.
NMOS X-OR/X-NOR Gates

Exclusive-OR and Exclusive NOR can easily be obtained using NMOS transistors. VA = High and VB = High
When both inputs are high, the output of the X-OR will
be low. The output of X-NOR will be high.
VA = High and VB = Low

When VA is high and VB is low, the output of the X-OR
will be high. The output of X-NOR will be low.
VA = Low and VB = High

When VA is low and VB is high, the output of the X-OR
will be high. The output of X-NOR will be low.
NMOS X-OR/X-NOR Gates

VA = Low and VB = Low
When both inputs are low, the output of the X-OR will
be low. The output of X-NOR will be high.

Determine the logic function for the following circuit.
NMOS Transmission Gates

NMOS device acts as a Switch by toggling the gate input voltage ON and OFF.
When the Gate voltage is high, the NMOS switch
is ON and when Gate voltage is low, the NMOS switch is OFF. This analysis offers the ability of transferring the driving logic voltage from one side of NMOS channel to the other side on CONDITION. NMOS switches are traditionally called Transmission Gates or Pass.

When VEN is high, the highly conductive path from NT output to the source exists that transfers the driving voltage VOUT to the input
VIN. This results in VOUT = VIN.

When VEN is low, the NT is cutoff and the input VIN is isolated from the output VOUT. Thus VIN is floating.

Example: Design a Multiplexer (4x1) using NMOS Transmission gates.

Digital Electronics: Arslan Qamar Malik Lecturer

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Arslan Qamar Malik Lecturer

Basic Logic Operations

Digital Logic Circuits Gates

Digital Logic Circuits Gates

Digital Logic Circuits States

Digital Logic Circuits Inverter

operation, this device is also called NOT gate.

It makes no difference if the inverting circle is

at the input or output.

Digital Logic Circuits NonInverter

Ideal Logic Inverter

Ideal Logic Static & Power Characteristic

Ideal Logic Transient Characteristic

Ideal Logic Input & Output Impedances

Ideal Logic Input & Output Impedances

Ideal Logic Input & Output Impedances

Inverter Voltage Transfer Characteristic

Inverter Voltage Transfer Characteristic

Inverter Voltage Transfer Characteristic

VOL < VIL

Logic Swing and Transition Width

output high and low voltage levels. VLS = VOH VOL

Noise in Digital Circuits

Noise in Digital Circuits

Noise in Digital Circuits

The high and low noise immunities are defined as the

Noise in Digital Circuits

Noise in Digital Circuits

gates logical 0 output state is Nlow = IOUT (low)/ IIN (low)

ton = turn on time

each of the output high and output low logic states.

Power Delay Product

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

Digital Logic operations can be implemented

using only MOSFETs.

the device is set as Metal Oxide Semiconductor FET.

region is now populated by the electrons under the Gate region.

N-channel enhancement-type MOSFET

N-channel enhancement-type MOSFET

N-channel enhancement-type MOSFET

N-MOSFET Modes of Operation

N-MOSFET Modes of Operation

N-MOSFET Modes of Operation

mode and ID is proportional to that increase.

N-MOSFET Modes of Operation

N-MOSFET Modes of Operation

N-MOSFET Modes of Operation

MOSFET: Device & Process Transconductance Parameters

MOSFET: Device & Process Transconductance Parameters

MOSFET: Device & Process Transconductance Parameters

MOSFET: Gate Capacitance per Unit Area (COX)

MOSFET: Gate Capacitance per Unit Area (COX)

MOSFET: Gate Capacitance per Unit Area (COX)

O = 8.854 x 10-12 F/m

Thus, Vt is a negative Threshold voltage.

Gate Oxide Capacitances

Source. CGB is the capacitance between Gate and Body.

Gate Oxide Capacitances

CG = CGS + CGD + CGB CG = L*W* COX

Body. CSB is the capacitance between Source and Body.

n-channel MOSFET is shown below.

region when VGS = +1V. What is the corresponding value of ID?

CG = CGS + CGD + CGB CG = LW COX