Basic VLSI Design

B LOKESHWAR Assistant Professor ECE Department RVR & JC College of Engineering

Outlines
Introduction Introduction MOSFETs NMOS CMOS

to IC Technology to MOS Technology

Modes

Fabrication Fabrication Fabrication

BiCMOS

Introduction to IC technology:

It is a circuit where all discrete components such as passive as well as active elements are fabricated on a single crystal chip Until 1950, electronic technology dominated by vacuum tube The first semiconductor chip held two transistors each

Introduction to IC technology
As

on increasing the number of components(or transistors) per IC the technology was developed as

SSI MSI LSI VLSI ULSI GSI

(Advances in VLSI)

Integrated Circuit Evolution

Year 1947 1950 1961 1966 1971 1980 1990 2000 Technology Invention of the transistor Discrete Components SSI MSI LSI VLSI USLI GSI Transistors/chip 1 1 10-100 100-1000 1000-20000 20000- 100000 100000 -1million More than 1 million Examples Tran and Diode Logic gates and flip flops Counters and registers 8 bit mp, ROM, RAM 16,32 bit mp Special purpose processors Embedded system, system on chip

VLSI(Very large scale integration)

is the process of created integrated circuits by

combining thousands of transistors into a single chip. VLSI begins in the 1970s when complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device.

Very large scale integration( Cont..)

VLSI chips are widely used in various branches of engineering like
Digital signal processing. Wireless LAN Bluetooth Bus interface via PCI,USB. Commercial electronics: TV sets, DVD. Computers and computer graphics. Automobiles, toys. Medicine: Hearing aids, implants for human body

Examples of VLSI

Moores Law
In 1965, Gordon Moore, an industry pioneer,

predicted that the number of transistors on a chip doubled every 18to 24 months.
He also predict that semiconductor technology will

double its effectiveness every 18 months

Many other factors also grow exponentially those are

clock frequency processor performance

Moores Law(Cont..)
Transistors count will be doubled for every 18 months

Introduction to MOS Technology

Whatever the IC (it may be simple logic gate,

microprocessor), that we are seeing outside can be manufactured using different MOS technologies.
The devices by which we can fabricate the different

types of ICs
These devices can be any type of the following:

Introduction to MOS Technology(Cont..)

Introduction to MOS Technology(Cont..)

Comparison of available Technologies

Introduction to MOS Technology(Cont..)

To know about each type of MOS technology, we just

look about to know transistor, types of transistors.

Transistor:
A transistor is a semiconductor device used to amplify and

switch electronic signals and power.

It is composed of a semiconductor material with at least

three terminals for connection to an external circuit.

Today, some transistors are packaged individually, but many

more are found embedded in integrated circuits.

Types of Transistors:
BJT: Problems: Low resistance Noise Problems: gate must be reverse biased(decreasing the conductivity) Called depletion mode of transistor) Channel width decreased

FET:

MOSFET
However, there is a FET that can be operated to

enhance the width of the channel(Enhancement Mode)

Such FET is called MOSFET(depends on mode of

operation.)
Dual Mode T MOSFE

ent m e c n a Enh OSFET M e d o M

MOSFET
Principle :
is that the source-to-drain current(SD current) is

controlled by the gate voltage, or better, by the gate electric field.

Heart: MOS Capacitor

MOS Capacitor

Figure 1: A Parallel Plate capacitor

Figure 3: The MOS capacitor with accumulation of holes

Figure 2: A corresponding MOS capacitor

If the electric field penetrates the semiconductor, the holes in the p-type semiconductor will experience a force toward the semiconductor interface

MOS Capacitor(Cont..)

Figure 1: Effect of +Ve gate bias

Figure 3: Due to larger +ve gate bias

Figure 2: Induced space charge region due to moderate +ve gate bias

MOS Capacitor(Cont..)
When a larger positive voltage is applied to the gate,

the magnitude of the induced electric field increases. Minority carrier electrons are attracted to the oxide semiconductor interface, as shown in Figure
This region of minority carrier electrons is called an

electron inversion layer. The magnitude of the charge in the inversion layer is a function of the applied gate voltage.

MOSFET(Cont..)
Therefore , apply the concepts of concepts of an inversion

layer charge in a MOS capacitor to create a transistor.

Such transistor is called Metal Oxide Semiconductor Field

Effect Transistor
Also called Insulated Gate FET Depending upon the type of mode, it can be classified into
Depletion mode MOSFET Enhancement Mode MOSFET

MOSFET(Cont..)
Enhancement Mode:
The term enhancement mode means that a voltage must

be applied to the gate to create an inversion layer.

For the MOS capacitor with a p-type substrate, a positive

gate voltage must be applied to create the electron inversion layer.(nMOS E-MOSFET)
For the MOS capacitor with an n-type substrate, a negative

gate voltage must be applied to create the hole inversion layer.(pMOS E-MOSFET)

MOSFET(Cont..)
Depletion Mode:
The term depletion mode means that a channel exists

even at zero gate voltage.

A negative gate voltage must be applied to the n-channel

depletion mode MOSFET to turn the device off.(much behave like n channel FET)
NMOS D-MOSFET PMOS D-MOSFET

MOSFET(Cont..)
Channel is established due to the implant even when

Vgs = 0 and the channel can be cut off by applying a negative voltage between the gate and source.

Enhancement Mode Transistor

Symbols:
Metal p-diffusion n-diffusion Poly silicon oxide p-Substrate n-Substrate depletion

NMOS E-Mode Transistor

Lightly doped p-type substrate Tow heavily doped N+ regions are diffused Thin Sio2 is grown over the entire surface
Figure: nMOS Enhancement mode transistor

Operation:
1. When Vgs < Vtn no inversion layer no conduction 2. When Vgs > Vtn electron inversion layer but no conduction since Vds=0 5. When Vgs > Vtn electron inversion layer conduction takes place but the transistor in non saturation region since Vds< VgsVtn 6. When Vgs > Vtn electron inversion layer conduction takes place but the transistor in saturation region since Vds >Vgs-Vtn Where Vgs-Vtn= Vds(sat)

Operation :

Operation(Cont..)

Characteristics:

Figure: VI Characteristics of n channel EMOSFET

Silicon wafer Fabrication

n-MOS fabrication process

1)

Process is carried out on a thin wafer (75 to 150 mm dia, .4mm thick)

Doped with boron impurity concentration of 1015/cm3 to make substrate

Substrate

n-MOS fabrication process

2) A layer of SiO2 grown all over the surface (1m thick) to protect.

SiO2

Substrate
RVR & JC College of Engineering- B

Photolithography
3) Then the oxidized wafer is covered with Photo resist.

Photo-Resist
SiO2

Substrate

Photolithography
4) Now the wafer is exposed to UV Light through a photo mask to define regions.

Photo-Mask
Photo-Resist
SiO2

Substrate

Photolithography
5.1) Now oxide which is unprotected from photoresist is etched away.

SiO2

Substrate

Photolithography
5.2) The rest of the photo resist is removed. Then the further fabrication process is carried out, say doping.

SiO2

SiO2

Substrate

Polysilicon on thin oxid

6)

Thin layer of SiO2(0.1m) grown and then polysilicon is deposited on top to form gate structur.
6)

Polysilicon layer consists of heavily doped polysilicon depositd by CVD.

SiO2

Poly Si
Thinox

Substrate

Metallization
7) Use mask to remove exposed area into which n-type impurities(phosphorus) are to be diffused to form source and drain.

SiO2

Poly Si n
Thinox

Substrate

Metallization
8) Again thinox is grown all over the surface and is then masked to expose selected areas of gate, drain and source to make Contact holes (cut)

SiO2

Poly Si n
Thinox

Substrate

Metallization
9) Finally, whole chip is metal deposited over its surface for required interconnection pattern.

SiO2

Poly Si n
Thinox

Substrate

nMOS Fabrication
Step 1:

Step 2:

Step 3:

nMOS Fabrication
Step 4:

Step 5:

nMOS Fabrication

CMOS fabrication
When we need to fabricate both nMOS and pMOS

transistors on the same substrate we need to follow different processes.

The three different processes are , P-well process ,N-well

process and Twin tub process.

CMOS fabrication
To accommodate both pMOS and nMOS devices, special

regions must be created in which the we place semiconductor is opposite to the substrate type.
These regions are called wells or tubes A p-well is created in the p-type substrate, alternatively an n-

well is created in the n-type substrate

CMOS fabrication
In the simple n-well CMOS fabrication technology
The nMOS transistor is crated in the p-type substrate and The pMOS transistor is crated in the n-well which is built in into the P-type

substrate

Similarly, in the p-well CMOS fabrication technology

The pMOS transistor is crated in the n-type substrate and The nMOS transistor is crated in the p-well which is built in into the p-type

substrate

N-well process- Flow chart

Main step in a typical n-well process

Formation of n-well regions Define nMOS and pMOS active areas Field and gate oxidations (thinox) Form and pattern polysilicon p+ diffusion n+ diffusion Contact cuts Deposit and pattern metallization Over glass with cuts for bonding pads

Poly silicon patterning

P-diffusion

Metallization

P-well process

Mask sequence. Mask 1: Defines the areas in which the deep p-well diffusion takes place. Mask 2: Defines the thin oxide region (where the thick oxide is to be removed or stripped and thin oxide grown) Mask 3: Its used to pattern the polysilicon layer which is deposited after thin oxide.

Mask 4: A p+ mask (anded with mask 2) to define areas where p-diffusion is to take place. Mask 5: We are using the ve form of mask 4 (p+ mask) It defines where n-diffusion is to take place.

Mask 6: Contact cuts are defined using this mask. Mask 7: The metal layer pattern is defined by this mask. Mask 8: An overall passivation (overglass) is now applied and it

also defines openings for accessing pads.

n-Well CMOS

Twin-tub COMS
well region.

n-type material and then we create both n-well and p-

Bi-CMOS
Driving capability of MOS transistors is less Bi-CMOS technology capable to drive large

capacitive loads.

Bi-CMOS
1. The npn transistor is formed an n-well & the additional p+ base region is located in the well to form the p-base region of the transistor. 2. The second additional layer, the buried n+ subcollector (BCCD) is added to reduce the n-well (collector) resistance & thus improve the quality of the bipolar transistor.

Comparison between CMOS and Bipolar technologies

CMOS
High input impedance Scalable threshold voltage High noise margin High packing density High delay sensitivity to load Low output drive current Low gm Bidirectional capability A near ideal switching device

Bipolar technologies
High power dissipation Low input impedance Low voltage swing logic Low packing density Low delay sensitivity to load High output drive current High gm Essentially unidirectional

Low static power dissipation

cost versus delay graph

CMOS for logic BiCMOS for I/O ECL for critical high

speed parts