System Verilog Testbench Language

David W. Smith Synopsys Scientist Synopsys, Inc.

Sample SOC and Testbench

DUT
10/100M Ethernet 1Gb Ethernet Ethernet MAC Ethernet MAC Ethernet MAC AHB APB Memory Controller Serial Ports Parallel Ports Testbench External Memory

CPU Core

RS232 model 1284 model Bluetooth model IR device model

10Gb Ethernet
USB model Proprietary model

USB

Control Logic

Bluetooth controller Infrared controller

Proprietary
Bus Controller

PCI Controller

Synchronous Interface Boundaries

PCI Model

Protocol Checkers for Interface

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David W. Smith

System with Multiple SOCs

Packet Switched Bus

Cache CPU Mem

AMBA FPU

Cache CPU Mem

AMBA FPU

Cache CPU Mem

AMBA FPU

SOC 1

DUT

SOC 2

SOC 3

At System Level Problem is Exacerbated Abstractions and Re-use are Necessary!

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Testbench Requirements
Stimulus Generation
Directed, Random, ATPG, ...

Checkers
Data Protocols

Structured Connection to Multiple Independent Interfaces

Interconnect Clocking Domain Protocol

Abstract Modeling
High-level data structures Dynamic Memory
> >

Memory Management Inter-process Synchronization, Control, and Communication

Re-entrant Processes

Single language for design (HDL) and verification (HVL) HDVL

Re-usability

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David W. Smith

Basic Types
Strings
arbitrary and dynamic length methods to manipulate and convert strings operators for comparison, concatenation and replication

Associative arrays
Indexed by integer, string, or class first(index), last(index), next(index), prev(index), delete(index), and exist(index) methods

Dynamic arrays
integer mem[*]; mem.size();

Linked Lists
doubly linked list of any data type iterator, modification, access methods

Classes, Objects and Methods

Object Oriented
>

Encapsulation, Inheritance, and Polymorphism

Objects referenced with handles (Safe Pointers)

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David W. Smith

Random Variables and Constraints

Test Scenarios Constraints Constraints Valid Inputs Specified as Constraints Declarative

Input Space
Design

Constraint Solver Find solutions

Valid

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David W. Smith

Random Variables and Constraints

rand, randc, and constraint added to class definition
class Bus; rand bit[15:0] addr; rand bit[31:0] data; endclass
constraint word_align { addr[1:0] == 2b0; }

Generate 50 data and quad-aligned addresses

Bus bus = new; repeat(50) begin integer result = bus.randomize(); end

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David W. Smith

Basic Additions
Wild card operators (=?= and !?=) Pass by reference Declaration: task tk( var int[1000:1] ar ); Use: tk( my_array ); // no & needed Argument default values and pass by name Declaration: task foo( int j = 5, int k = 8 ); Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9)); Alias for nets
Short nets in a module

Dynamic Memory
Objects, threads, strings, dynamic and associative arrays Automatically Managed

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David W. Smith

Process Control/Synchronization
Verilog thread support from forkjoin with continuation when all threads complete SV threads use forkjoin with continuation control
all any none
all

Threads execute until a blocking statement

wait for event, mailbox, semaphore, variable change, ...

any priority

none

3.0 process

Enhanced events (value and duration, passed as arguments) Threads are controlled by
$terminate $wait_child $suspend_thread $exit

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David W. Smith

Clocking Domain
A clocking domain defines a synchronous interface for testbench and properties Every clocking domain has only one clock event Sample and drive timing specified with respect to clock A signal may appear in multiple clocking domains
Input - multiple samples Output default bus resolution

Clocking domain creates a scope

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Synchronous Interfaces: Clocking

Race-free cycle and transaction level abstraction device
bus clk enable full data[7:0] empty

Synchronous Interface

clocking bus @(posedge clk);

Clocking Event clock Default I/O skew Hierarchical signal

default input #1ns output #2ns;

input inout output output #6ns endclocking enable, full; data; empty; reset = top.u1.reset;
Override Output skew
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Testbench Uses: bus.enable bus.data ...

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Testbench Program Block

Purpose: contains testbench verification code program is similar to a module Only one implicit initial block Special semantics Execute in verification phase

design clocking verification read_only

program name ( port_list ); declarations (class, type, function, clocking...) statements endprogram
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System Verilog Testbench

Testbench

Verification Extensions
Aliases Basic Types

Testbench Specific

Random Constraints
Process Control/Synchronization References

Clocking Domains
Program Block

5 December 2003

David W. Smith

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