Makefile Concept

Prepared by: Shah Het. Prajapati Arjun. Rathod Jatin. Poshiya Ujas. 1 Shah Dipen.

Origin of Makefile
It was originally created by Stuart Feldman in 1977 at Bell Labs. In 2003 Dr. Feldman received the ACM Software System Award for the authoring of this widespread tool. Before Make's introduction, the Unix build system most commonly consisted of operating system dependent "make" and "install" shell scripts accompanying their program's source. Being able to combine the commands for the different targets into a single file and being able to abstract out dependency tracking and archive handling was an important step in the direction of modern build environments.

What is Makefile
A Makefile can be the collective memory of commands necessary to build or manage a software project. There are several flavours and variants of make.
A Makefile contains targets, dependencies,and commands. make is a simple and useful tool that compares the dependencies in the Makefile, with respect to the source file time stamps, executing the given commands to create an up-todate dependent.

Why should I use a Makefile?

When developing software the usual cycle is to edit, compile, execute, debug and repeat until all the bugs are found or when satisfied. This involves lots of repetitive steps.
just type make

When should I use a Makefile?

When there is many files to handle. If the code is expected to be built on different machines. There are special handling steps. If you expect to rebuild your executable at some later point the Makefile retains the memory of the needed steps.

Project structure
Project

structure and dependencies can be represented as a

DAG (= Directed Acyclic Graph)

Example

:
contains 3 files sum.c, sum.h should be the file sum

Program main.c.,

sum.h

included in both .c files

Executable

sum (exe)

main.o

sum.o

main.c

sum.h

sum.c

Make operation
Project Target We

dependency graph is created.

of first rule should be created

go down the DAG to see if there is a target that should be

recreated. This is required when the target file is older than one of its dependencies
In

this case we recreate the target according to the action

specified, on our way up the tree. Consequently, more files may need to be recreated
If

something was changed, linking is performed

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Makefile Syntax

Rules: It refers to the collection of a target , possible dependencies and command to execute.

Targets: A target is what to build and occurs on left of colon in syntax.

Dependencies: These are the files needed to run the target.

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 Target name can be almost anything: just a name

Targets

a filename
a variable There can be several targets on the same line if they depend on

the same things.

A target is followed by a colon :

and then by a list of dependencies, separated by spaced

The default target make is looking for is either all or first one in the file.
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Targets - continued
Another common target is clean
Developers supply it to clean up their source tree from temporary files, object modules, etc.

Typical invocation is:

make clean You are required to supply another target, called run, so that

it makes sure your application is compiled and run just by

typing: make run.
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Dependencies
The list of dependencies can be:

Filenames
Other target names Variables

Separated by a space.
May be empty; means build always.

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Dependencies - continue
Before the target is built: its checked whether it is up-to-date (in case of files) by

comparing time stamp of the target of each dependency; if the

target file does not exist, its automatically considered old. If there are dependencies that are newer then the target, then the target is rebuild; else untouched. If you want to renew the target without actually editing the dependencies, touch them with the touch command. If the dependency is a name of another rule, make descends recursively (may be in parallel) to that rule.
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makefile
sum: main.o sum.o gcc o sum main.o sum.o main.o: main.c sum.h gcc c main.c

Rule

Rule

sum.o: sum.c sum.h

gcc c sum.c

Rule
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Target

Rule syntax
Dependencies

main.o: main.c sum.h gcc c main.c

Rule

Tab!!!

Action(s)

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Make operation
File sum main.o sum.o main.c sum.c sum.h Last Modified 10:03 09:56 09:35 10:45 09:14 08:39

Which targets will be recreated?

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Main.c

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a.c

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b.c

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Makefile

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execution

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Running the program.

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Some important points...

Must copy header files to the current directory. There must be only one main function in all files. Enter ./target_name to run. Do not use make -t after you make a change. Your c files can be in any folder.You only need to mention the paths.

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Extensions to make.

-C to run Makefile in other directory

make -C /home/proj2

-n to dry run the program.(changes will not come to effect) -d print debugging information. -f use file1 as a makefile.

Make -f file1

-i ignore errors while remaking a file. -k keep going till possible. -t consider file as up to date.

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Shortcuts
We

can compress identical dependencies and use built-in macros to get another (shorter) equivalent makefile :

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$@ name of target $? name of depended changed $< name of the first dependent $^ names of all dependents $+ replace all dependencies with

duplicates.

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$(@D) The directory part of the file name of the target, with the trailing slash removed. If the value of $@ is dir/foo.o then $(@D) is dir. This value is . if $@ does not contain a slash. $(@F) The file-within-directory part of the file name of the target. If the value of $@ is dir/foo.o then $(@F) is foo.o. $(@F) is equivalent to $(notdir $@) $(<D) $(<F) The directory part and the file-within-directory part of the first prerequisite.

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$(^D) $(^F) Lists of the directory parts and the file-within-directory parts of all prerequisites. $(+D) $(+F) Lists of the directory parts and the file-within-directory parts of all prerequisites, including multiple instances of duplicated prerequisites. $(?D) $(?F) Lists of the directory parts and the file-within-directory parts of all prerequisites that are newer than the target.

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Any questions???

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