DESIGN CONVENTION

Central Processing Unit (CPU)

The CPU has four main components: 1. The Control Unit 2. Arithmetic Logic Unit 3. The Register Set 4. An Internal Bus System. Arithmetic Logic Unit, Register Set and Bus System are collectively known as datapath unit.

INTRODUCTION
Any HDL is based on the fact that most digital system can be partitioned into a control section and data path section. The control circuit causes register transfer to take place in the data section by sending signals on a set of control lines. In some circuits the sequencing of control will be influenced by branching information fed back from the data section.

Data\Control Partition
Data Registers and Logic

Data Input

Data Output Branching information

Control Signals

Control Input

Control Sequential Circuit

MICRO OPERATIONS
A micro operation is an elementary operation performed on the information stored in one or more registers in one clock cycle. For examples shift, count, clear, load

There are four categories of the most common micro operations: 1. Register transfer. 2. Arithmetic. 3. Logic. 4. Shift.

 The basic arithmetic micro operations are addition, subtraction, increment, decrement, and shift. Example of addition: R3 R1 +R2. Subtraction is most often implemented through complementation and addition. Adding the contents of R1 to the 2s complement of R2 is equivalent to subtracting Multiply and divide are not included as micro operations since it cant be executed in one clock pulse.

REGISTER TRANSFER NOTATIONS

Much of the activity of digital system consist of transferring bits of information from one register to another. For example: A B; A B + C; Since bits of information are often treated uniformly, these logical computation can be expressed as vector notation. It is quiet possible to view a digital system as a collection of registers among which data may be transferred.

Register Transfer Language

The symbolic notation used to describe the micro operation transfers among register is called a register transfer language A convenient tool for describing the internal organization of digital computers Can also be used to facilitate the design process of digital systems.

 Capital letters and Numbers are used to denote Registers. For examples: MAR2, IR Parentheses () is used denote a part of registers. For example PC(H), ACC(3:0). Arrow denotes transfer of information among register. For example A B. Comma , separates two micro operation. For example A B, C D Two micro operation separated by comma are executed on the same clock cycle.

RTL Notations

Conditional Transfer: If the transfer is to occur only under a predetermined control condition, designate it by If (P = 1) then (R2 R1) or P: R2 R1, where P is a control function that can be either 0 or 1. Every statement written in register transfer notation implies the presence of the required hardware.

Electronic Realization of Register Transfer

Two methods are popular for register transfer:
1. Gating method of Register Transfer. 2. Busing method of Register Transfer.

The majority of register transfers in a digital system are clocked, i.e. synchronized by a system master clock. Mostly D-flip-flop or JK-flip-flop are used for realization of register transfers. Both control section and data section are synchronized with clock. All logic level changes and transfers are assumed to take place at the time of leading edge (+ve triggered) or trailing edge (-ve triggered) clock pulse. Often, control signal is ANDed with the clock in gating method of register transfer.

CONTROL SEQUENTIAL CIRCUIT

CSL
CLOCK CSP

CSL

CLOCK

CSP
Old Data in BR New Data in BR

Clocked transfer between two register (BR<- AR).

AR0
Q QBAR

AR1
Q QBAR

AR2
Q QBAR

CSL

CSP

CLOCK
D C D C D C

BR0

BR1

BR2

Q QBAR

Q QBAR

Q QBAR

Register Transfer Contd

Very often there may be more than one vector to be transferred into a same register. This transfer may take place in separate step or may be expressed in the same step as a conditional transfer. Bank of AND gates are used where each flip flop of the register is gated with the control signal. For example, Implement a circuit which performs the following expression:
If (CSL1= 1) then (CR AR) If (CSL2= 1) then (CR BR) AR, BR, CR are 4-bit register. It is assumed that CSL1 and CSL2 can never be 1 simultaneously.

AR
CSL1
CSL2

BR

CLOCK
C

D C

D C

CR0

CR1

CR2

Q QBAR

Q QBAR

Q QBAR

AR
Q Q Q Q Q Q

BR
Q Q

CSL1

CSL2
D
C D

CLOCK
D
C D

CR3

CR2

CR1

CR0

Problem: Implement the following logic by using gating method of register transfer.
If (CSL1= 1) then (BR 0, 0, 0, 0) If (CSL2= 1) then (BR 1, 1, 1, 1) If (CSL3= 1) then (BR AR) AR, and BR are 4-bit register.

NOTE
In register transfer through gating method, data transfer operation occur among register, and the transfer operation is synchronized with a common system clock. Mostly D-flip-flop are used for realization of register transfer operation. The content of every bit of each source register is ANDed with the controlling signal which initiates transfer from that source register provided the number of source register is more than one. For ANDing a bank of AND gate is required.

BUSING
Many times, transfers of information among several registers is required. The direct extension of gating method results highly expensive circuits, since bank of AND gates increases drastically. An alternate method that is generally less expensive in the use of an interconnection bus also known as busing method of register transfer. The number of wires will be excessive if connections are made between the outputs of each register and the inputs of the other registers. A more efficient scheme for transferring information in a system with many registers is to use a common bus. Transfer of data through Bus is a two step process.

Simplified Busing Method of Register Transfer

AR
BUS

BR DR

CR

AR
Q Q Q Q Q Q

BR
Q Q

CSL1

CSL2

BUS CSL1 CLK

CR

DR

CSL2 CLK

Busing Contd
Transfer of data through Bus is a two step process. Both steps are accomplished in one clock cycle. The first step routes the data to the output of the bus. The data remains at the output of the bus as long as control level remains 1. In the second step, the data at the output of the bus are copied in the destination register, in the same clock cycle.

Possible Hardware Saving.

Suppose, it is desired that a path be made available for the transfer of information from one of n register to any one of m destination register. In gating method, nm banks of AND gate will be required together with m banks of OR gate. If we assume b bit in each register then total number of gates required = (nm + m) * b. Number of gates using Busing = (n+ 1) * b.

Tri State Buffer(Tri-state Logic)

A three-state buffer is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-impedance state behaves like an open circuit which means that the output is disconnected and does not have a logic significance. It is distinguished from a normal buffer by having both a normal input and a control input.

Tri State Buffer Contd

Input A Output B

Control input C
Symbolic Notation

If (C==1) then B =A. If (C==0) then device goes to high impedance state.

 A program will always have a sequence of instruction mainly Register Transfer Operations. For example: #1 MOV A B; #2 MOV D A + C; #3 if ( q ==1) then #4 ADD D, A; For each instruction, one control signal has to be provided by the control unit. Hence a sequence of control signal has to be provided for execution of a program. The generation of this control signal and feeding this signal into the data path unit is known as sequencing of control.

SEQUENCING OF CONTROL

ELECTRONIC REALIZATION OF CONTROL UNIT

Realization of control unit is possible with a varying amount of combinational logic and flip flop. Realization of control unit is separated from the realization of datapath unit. For realization of hardwired control unit one flipflop per state model (per instruction) is required. For realization of micro-programmed control unit, n flip flop is required for instructions 2n.

CONTROL UNIT REALIZATION

Inst. #1 D1 Q1 C CLOCK #1 AB #2 C D (a, b)/(4, 3) #3 C A +B #4 D A+B Inst. #2 a D2 Q2 C D4 Q4 C D3 Q3 C
Inst. #4

Inst. #3

Start
CLOCK

Q1 Q2

Q3
Q4

If (a=1)
If (b=1)

 Problem: Show the control unit realization of the following AHPL code: #1. R X (abar & bbar, a, abar & b)/(1, 2, 4) #2. R R1 (bbar)/(4) #3. R R3 #4. Z=R (1)

 Conditional branch offers a method of choosing between two or more transfer which might be accomplished at a particular point in time depending on which of a set of input or feedback control values are 1. Suppose, for example A B if (a=1) or D C if (b=1). For realization of its control unit, sequence of instruction has to be written. #1 Inst. (a, b)/(2, 3) #2. AB (4) #3. DC

CONDITIONAL TRANSFER

Conditional Transfer Notation

A B (Unconditional) A*aB A B* a (A!B!C)*(f, g, h) D (A!B!C)*(a, b, c) (D!E!F)*(d, e, f) Asterisk (*) in the right of an register signifies if condition. Above example can be represented in AHPL as A*a B; D*bC

 An asterisk or a condition on the left side of the transfer expression always indicates that a control pulse will arrive at the clock inputs to the flip-flop of the destination register iff condition is satisfied. For ex: (B!C)*(b, c) A Conditions on the right side of the transfer expression specify busing network for the data vector to be selected to the right side of the transfer expression For ex: A(B!C)*(b, c)

A B
Inst. #1

Inst. #4

D2 Q2 C
D3 Q3 C

D1 Q1 C

D4 Q4 C

C D
Branch and Convergence

Inst. #1

A B or C D?
D4 Q4 C

D1 Q1 C

D2 Q2 C

A B C D
Conditional Transfer
Inst. #1

a D1 Q1 C D2 Q2 C

b D4 Q4 C