D ALGORITHM

ATPG
Automatic test-pattern generation (ATPG) is the process of generating patterns to test a circuit, which is described strictly with a logic-level netlist (schematic.) These algorithms usually operate with a fault generator program, which creates the minimal collapsed fault list ATPG algorithms are multi-purpose,
they can generate circuit test-patterns, They can find redundant or unnecessary circuit logic, they can prove whether one circuit implementation matches another circuit implementation

Specific-Fault Oriented Test Generation

Three Approaches
Internal Line Values Assigned ( D Algorithm) (Roth-1966) Input Values Assigned (PODEM) (Goel 1981) Input and Internal Values Assigned (FAN) (Fujiwara)

ROTHS 5-VALUED ALGEBRA

DEFINITIONS
Back-trace: Moving a goal value backward in the circuit space from the output of a primitive element to one or more of its inputs until a primary input is reached. Backtrack: Retracing in the search graph to resolve a conflict by trying alternative assignments at previously assigned nodes. D frontier: The set of gates closest to primary outputs that have one or more D values on their inputs and an X value on their output. Fan-out: Any circuit node that drives more than one primitive element. Fault: A failure in a circuit that causes its logical behavior to differ from that of the circuit without the failure. Most faults are assumed to be static; that is, they are present from the time they first occur until the circuit is repaired or replaced. Fault coverage: The number of faults expressed as a percentage of all faults that are detected by a set of test patterns.

DEFINITIONS (Contd.)
Fault propagation: Moving the effect of a fault to a primary output by assigning values to the nodes in the search space. Fault sensitizing: Finding a set of primary input values that causes the fault site in the good circuit to have a value opposite to the faulty value (s-a-0 or s-a-1). Faulty circuit: A replica of the original circuit with each fault site replaced by the particular fault model. The most common fault model is the single stuck-at fault. Free line: A circuit node that has no re-convergent fan-out nodes among its predecessors. Good circuit: The original circuit with no faults present. Headline: A free line that drives a re-convergent fan-out node. Also called the root of a tree of free lines in the circuit

DEFINITIONS (Contd.)
Implication: Determining the unique values implied by already assigned values. This process can cause both forward and backward assignment of values. Forward Implication : A forward implication results when the inputs to a logic gate are significantly labeled so that the output can be uniquely determined. Backward implication : It is the unique determination of all inputs of a gate for given output and possibly some of the inputs. Justification: The process of finding a set of primary input values that cause a node to take on the desired value; essentially the same as back-trace with conflict resolution. Primary inputs: The externally accessible input pins of a circuit through which we can inject logical values into the circuit. Primary outputs: The externally accessible output pins of the circuit through which we can observe logical values from the circuit.

DEFINITIONS (Contd.)
Re-convergent fan-out: A fan-out node, two or more of whose branches eventually are used as inputs to the same element. The element (one or more) at which the branches re-converge is called the point of re-convergence. Redundant fault: A fault that because of redundancy in the circuit cannot be detected by any static test. Also known as an undetectable fault. Sensitized path: A path that begins at the fault site and ends at a primary output. A change in the logical value of the fault site changes the logical value at the output. Single-fault assumption: The assumption that one and only one fault is present in a given circuit at a time. Stuck fault: A fault model in which the fault site has a permanent binary value (either 0 or 1). The value is assumed to be caused by the presence of a fault. Test: An input pattern that will cause one or more circuit outputs to differ, depending on whether a given fault is present or absent. A test may detect more than one fault, and a set of tests is required to detect all detectable faults.

FAULT CONE & D-FRONTIER

D ALGORITHM -- ROTH IBM (1966)

SINGULAR COVER

D-CUBE

D INTERSECTION

PROPAGATION D-CUBE

IMPLICATION PROCEDURE

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