Sequential Circuits &

Flip-Flops
•Basic Latch
•Gated SR & D Latches
•D, T & JK Flip-Flops
•Metastability
 Objectives
• Upon completion of this chapter, student should
be able to:
– Describe the operation and use of latch and flip-flops (S
R, D, J K)
– Draw the flip-flops logic symbol.
– Draw timing diagram based on flip-flop operation.
– Recognize the difference between a latch and a flip-
flop.
– Understand the flip-flops operating characteristics
– Apply flip-flops in basic applications.
 Summary of previous
week
• Decoder
• 7 segment display
Function
• Encoder Truth table

• Multiplexer
• Demultiplexer
 Sequential Circuits
• Combinational – output depends only on the input.
– Do not have memory
– Cannot store state
• Sequential – output depends on input and past behavior.
– Require use of storage elements.
– Contents of storage elements is called state.
– Circuit goes through sequence of states as a result of changes
in inputs.
Sequential Circuits Types
• Synchronous
– State changes
synchronized by one or
more clocks
– Easier to analyze because
can factor out gate delays
– Set clock so changes
allowed to occur before
next clock pulse
• Asynchronous
– Changes occur
independently
– Potentially faster
– Harder to analyze
Simple Memory Elements
A B

• A simple memory element: feedback will hold value

Reset

Set Q

• A memory element with NOR gates:

Use Set/Reset to change stored value
 SR Latch
• Basic storage made from gates
• Rearrangement of memory element from previous slide!

R Function Table
Q S Q
S R Q Function
0 0 Qo Hold R Q

S
Q 0 1 0 Reset
Graphical symbol
1 0 1 Set
1 1 ? Not allowed

• If S & R both 1 at same time, Q = Q’ = 1

 SR Latch SR
0X

Detailed Function
0
Table
S R Q Q+
Excitation Table
0 0 0 0
Q Q+ S R 01 10
0 0 1 1
0 0 0 X
0 1 0 0
0 1 1 0
0 1 1 0
1 0 0 1
1 0 0 1 1
1 1 X 0
1 0 1 1
1 1 0 X X0
1 1 1 X State Transition
Diagram:
The excitation table in
Excitation Table: What are the necessary graphical form
inputs to cause a particular kind of change in
state?
 S R Latch
• Similar – made from
NANDs Function Table
S R Q Functio
n
1 1 Qo Hold
1 0 0 Reset
0 1 1 Set
0 0 ? Not
allowed
 Gated SR Latch
• Add Control Input
– Typically, control signal is referred to
as a clock
• Clock controls when state can change
EN

EN
 Gated SR Latch
1
ENC
0
1
R
0
S Q
1
S EN
C
0
R Q
1
Q ?
0
Graphical symbol
1
Q ?
0
Time
 Gated D Latch
• No illegal state
S
D EN
(Data) Q

EN

Q
R

(a) Circuit
 Gated D Latch
D Q

CEN Q

(c) Graphical symbol

t1 t2 t3 t4

EN

Time
(d) Timing diagram
 D Latch 0

0
Detailed
Excitation
Function Table
Table
D Q Q+ Q Q+ D
0 1
0 0 0 0 0 0
0 1 0 0 1 1
1 0 1 1 0 0
1 1 1 1 1 1 1

State Transition
Diagram
Standard Symbols – Latches

EN EN

Circle at input indicates negation

 Flip-Flops
• Ensure only one transition
• Two major types
• Master-Slave
– Two stage
– Output not changed until clock disabled
• Edge triggered
– Change happens when clock level changes
 Edge-Triggered Flip-
Flops
• Synchronous input
– Change state either at positive edge or
negative edge of a clock pulse.
• Edge triggered S-R flip flop
S-R Flip-Flop
 S-R Flip-Flop
• Edge-triggering-
pulse transition
detector,
produces a very
short-duration
spike during the
transition of the
clock pulse.
Symbols – Edge-
Triggered

Arrow indicates edge trigger

 D Flip-Flop
1 P3

P1
2
5 Q

Clock

P2 6 Q
3 D Q

Clock Q

4 P4 (b) Graphical symbol

D

(a) Circuit
A positive-edge-triggered D flip-flop
D Flip-Flop
 D Latch versus D Flip-
Flop
D D Q Qa
Clock

Clock EN Q
Clk Qa D

Qa
D Q Qb
Qb
Q Qb
Qc

D Q Qc (b) Timing diagram

Q Qc

(a) Circuit

Comparison of level-sensitive and edge-triggered

devices
 JK Flip-Flop

(a) Circuit

J K Q ( t + 1)
0 0 Q (t) J Q
0 1 0
1 0 1 K Q
1 1 Q (t )

(b) Truth table (c) Graphical symbol

JK Flip-Flop

(b) Timing Diagram

 JK Flip-Flop
SR
0X

0
Detailed
Function
Table Excitation
Table
J K Q Q+
Q Q+ J K X1 1X
0 0 0 0
0 0 0 X
0 0 1 1
0 1 1 X
0 1 0 0
1 0 X 1 1
0 1 1 0
1 1 X 0
1 0 0 1
X0
1 0 1 1
1 1 0 1 State Transition
1 1 1 0 Diagram
 Asynchronous Inputs
• State of the flip flop change independent of
the clock.
 Flip-flops Operating
Characteristics
• Propagation delay time
– tPLH from triggering edge of clock to LOW-to-
HIGH output transition.
– tPHL from triggering edge of clock pulse to
HIGH-to-LOW output transition.
– tPLH from leading edge of preset input to LOW-
to-HIGH output transition.
– tPHL from leading edge of clear input to HIGH-
to-LOW ouput transition.
 Flip-flops Operating
Characteristics
• Set-up time,ts
– Minimum interval required for the logic level to be maintained
constantly on the inputs prior to the triggering edge of clock
pulse.
• Hold-time, th
– Minimum interval required for the logic levls to remain on the
inputs after the triggering edge of the clock pulse.
• Maximum clock frequency response
– Highest rate at which a flip-flop can be reliably triggered
• Pulse width, tw
– Minimum pulse widths for reliable operation.
• Power dissipation
– Total power consumption of the device.
– P=VCC X ICC
 Flip-flops Applications
• Parallel data storage
 Flip-flops Applications
• Frequency division
 Flip-flops Applications
• Counting
• THANK YOU FOR
LISTENING…………………