A CIRCUIT LEVEL IMPLEMENTATION OF CDMA BASED DPU USING 65 NM CMOS TECHNOLOGY

POOJA VERMA Roll No- 1270679 Branch- M.Tech. VLSI Design

Supervisor Mrs.Rachna Manchanda Assistant Professor

INTRODUCTION
RFID SYSTEMS

RFID tag system is paid attention to as an identification source.Each RFID Tag is attached to some object whose information is needed at the user end.

With unique ID of RFID Tag a user identifies the object provided with RFID tag
and derives informaion about object.

One of the important application of RFID technology is in estimating the presence

of an object within its communication range.

RFID Tags can also be fitted to the persons working in the company for identifying them for security purpose.

TRANSCEIVER ARCHITECTURE
Proposed wireless application system prototype consist of two subsystem, namely an RFID Transmitter (Tag) and an RFID Receiver (Reader), along with wireless communication path .
RFID TRANSMITTER

A battery less,active self Powered RFID Tag can transmit N bit wireless identification code to the receiver,enabling the user to transmit their identity automatically to the reader as the user walks

Block diagram of RFID Tag

RFID RECEIVER

At the reader side ,the CDMA based energy detection receiver is implemented. The model can be applied to the multiple Tags that are transmitting their unique

identification code at different assigned modulation frequencies,but at same

time.

Block Diagram of RFID Receiver

Role of VLSI in proposed system

Low power ,highly compact and fast circuits are the basic requirements of rfid applications.

Increasing demand of such circuits have fuelled much research into the different styles of VLSI design which can be adressed at different design levels such as architectural,circuit, layout,and process technology level.

The proposed digital processing unit is designed at circuit level . By means of proper choice of logic style and process technology considerable effort can be made made in fields like area power and speed .

OBJECTIVES

To make an area efficient design for highly compact low power digital
processing unit of RFID tag receiver.

To achieve low power dissipation and less delay for high performance of system. This has to be done without trading of driving capabilities and reliabilities.

To efficiently utilize battery less, active ,self powered RFID tag, to identify the person to which tag is attached.

DESIGN METHODOLOGY
o

The RFID Receiver can be divided into two parts Analog front end (AFE)

Digital processing unit (DPU)

The present work includes only realization and analysis of digital processi unit only.

The proposed DPU is based on hybrid CMOS design style using 65 nm CMOS process technology. The design consist of 4 modules 1. DETECTOR 2. CORRELATOR 3. INTEGRATOR 4. DISPLAY UNIT

Four of them are implemented into circuit level with proper W/ L ratio.

Block diagram of digital processing unit

The

layout design will be done using cadence/ microwind 3.5.

CONCLUSION
To design an area efficient DPU of RFID receiver without compromising performance.