You are on page 1of 27

STRUCTURAL MODELLING

Component Declaration
component HALFADDER
port (A, B : in bit;
SUM, CARRY : out bit);
end component;
Port _Modes
• in:signal values are read-only
• out:signal values are write-only
multiple drivers
• buffer:comparable to out
signal values may be read, as well
only 1 driver
• inout:
bidirectional port
Hierarchical Model Layout
• HDL allows for a hierarchical model layout,
which means that a module can be assembled out
of several submodules. The connections between
these submodules are defined within the
architecture of a top module.
• As you can see, a fulladder can be built with the
help of two halfadders (module1, module2) and an
OR gate (module3).

• A purely structural architecture does not describe


any functionality and contains just a list of
components, their instantiation and the definition
of their interconnections.
• entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
signal W_SUM, W_CARRY1, W_CARRY2 : bit;
component HALFADDER
port (A, B : in bit;
SUM, CARRY : out bit);
end component;
component ORGATE
port (A, B : in bit;
RES : out bit);
end component;
begin
• As the fulladder consists of several
submodules, they have to be
"introduced" first. In a component
declaration all module types which will
be used, are declared.
• This declaration has to occur before the
'begin' keyword of the architecture
statement. Note, that just the interface
of the modules is given here and their
use still remains unspecified.
• The component declaration is therefore
comparable with a socket definition, which
can be used once or several times and into
which the appropriate entity is inserted later
on. The port list elements of the component
are called local elements.
• In this case, only two different sockets,
namely the socket HALFADDER and the
socket ORGATE are needed. Arbitrary
names may be chosen for the components,
yet it is advisable to use the name of the
entity that will be used later on.
MODULE1: HALFADDER
port map( A, B, W_SUM, W_CARRY1 );
MODULE2: HALFADDER
port map ( W_SUM, CARRY_IN,
SUM, W_CARRY2 );
MODULE3: ORGATE
port map ( W_CARRY2, W_CARRY1,
CARRY );
end STRUCT;
• Socket generation
• How many do I need?
• Instantiation in definition part of
architecture (after 'begin')
• Places socket on PCB
• Wires signals:
• default: positional association
entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;

architecture STRUCT of FULLADDER is

component HALFADDER
port (A, B : in bit;
SUM, CARRY : out bit);
end component;
...
signal W_SUM, W_CARRY1, W_CARRY2 : bit;

begin

MODULE1: HALFADDER
port map ( A => A,
SUM => W_SUM,
B => B,
CARRY => W_CARRY1 );
...
end STRUCT;
• Named association:
• left side: "formals"
• (port names from component declaration)
• right side: "actuals"
• (architecture signals)
• Independent of order in component
declaration
• It is the task of the VHDL configuration to
link the components to entity/architecture
pairs in order to build the complete design.
In summary: A component declaration
provides a certain kind of socket that can be
placed on the circuit as often as necessary
with component instantiations. The actual
insertion of a device into the instantiated
sockets is done by the configuration.
Configuration: Task and
Application
entity FULLADDER is
...
end FULLADDER;

architecture STRUCT of FULLADDER is


...
end STRUCT;
configuration CFG_FULLADDER of
FULLADDER is
for STRUCT -- select architecture
STRUCT
-- use default configuration rules
end for;
end configuration CFG_FULLADDER ;
Configurations

• Selects architecture for top-level entity


• Selects entity/architecture pairs for instantiated
components
• Generates the hierarchy
• Creates a simulatable object
• Default binding rules:
• selects entity with same name as component
• signals are associated by name
How to-configurations
entity A is
port(A, B: in bit;
SUM, CARRY: out bit);
end A;

architecture RTL of A is
···
How to?
entity B is
port(U,V: in bit;
X,Y: out bit);
end B;

architecture GATE of B is
···
entity FULLADDER is
port(A, B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
component HALFADDER
port(A, B: in bit;
SUM, CARRY: out bit);
...
signal W_SUM, W_CARRY1, W_CARRY2: bit;
signal W_SUM, W_CARRY1, W_CARRY2: bit;

begin
MODULE1: HALFADDER
port map (A, B, W_SUM, W_CARRY1);

MODULE2: HALFADDER
port map(W_SUM, CARRY_IN,
SUM,W_CARRY2);
..
end STRUCT;
• configuration CFG_FULLADDER of FULLADDER is
for STRUCT
for MODULE2: HALFADDER
use entity work.B(GATE);
port map ( U => A,
V => B,
X => SUM,
Y => CARRY );
end for;
for others : HALFADDER
use entity work.A(RTL);
end for;
end for;
end CFG_FULLADDER;
• Entity/architecture pairs may be selected by
use of
instance names
• 'all': all instances of the specified
component
• 'others': all instances not explicitly
mentioned
• If the port names differ
=> port map clause
• Possible to reference an existing
configuration of a submodule