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GENERICS

• Used to pass information into a design


description from an environment
• E.g. rise and fall delays ,size of ports
• Used to construct parameterized models
Entity AND_GATE is
Generic (N:NATURAL);
Port (A:in BIT_VECTOR (1 to N);
Z:out BIT);
Architecture EXAMPLE of AND_GATE is
begin
process(A)
variable AND_OUT :BIT;
Begin
AND_OUT :=‘1’;
for K in 1 to N loop
AND_OUT :=AND_OUT and A(K);
Exit when AND_OUT =‘0’;
End loop;
Z<=AND_OUT;
End process;
End EXAMPLE;
–Here the size of the input port
has been modeled as a generic.
• An entire class of AND gates with a
variable number of inputs has the same
behavioral model
• The value of the generic may be specified
• In
• 1.Entity declaration
• 2.Component declaration
• 3.Component instsntiation
• 4.Configuration specification
• 5.Configuration declaration
• The value of a generic may be specified in
the entity declaration .
• This is the default value
• It can be overridden by others
Entity xor2 is
Generic (gate_delay:Time:=2 ns);
Port (In1 ,In2 :in std_logic;
Z: out std_logic);
End entity xor2;

Architecture beh of xor2 is


Begin
Z<=(In1 xor In2) after gate_delay;
End architecture beh;
Component xor2 is
Generic (gate_delay:Time:= 3 ns);
Port (x,y :in std_logic;
Z: out std_logic;
End component xor2;

Component and2 is
Generic (gate_delay:Time:=5 ns);
Port (x,y :in std_logic;
z: out std_logic);
End component and2;
Begin
EX1:xor2 generic map (gate_delay=6 ns);
Port map (x=>x, y=>y, z =>sum);
A1:and2 generic map(gate_delay=>3 ns);
port map( x=>x,y=>y,z=>carry);
End architecture generic_delay;

If generic values are provided in component


declarations and component
instantiations, the value given by the
generic map is used.
• Suppose we specify the value of
‘gate_delay ‘ in the generic map of a half
adder .
• If the components of this (xor ,and etc)
use this same parameter ,then this value
will be passed to the lower level entities.
• It will also override the values of
gate_delay specified in their entity
declarations
Entity generic_reg is
Generic(n:positive:=2);
Port (clk,reset,enable:in std_logic;
d:in std_logic_vector (n-1 to 0);
Q:out std_logic_vector (n-1 to 0);
End entity generic_reg;
Configuration

• A VHDL description may consist of many


design entites, each with several
architectures, and organized into a design
hierarchy. The configuration does the job
of specifying the exact set of entities and
architectures used in a particular
simulation or synthesis run.
• A configuration does two things.
• Firstly, a configuration specifies the
design entity used in place of each
component instance (i.e., it plugs the chip
into the chip socket and then the socket-
chip assembly into the PCB).
• Secondly, a configuration specifies the
architecture to be used for each design
entity (i.e., which die).
• Multiple views of the same
entity may be present.
• Configuration specifies which
view to use in
simulation/synthesis
Configuration is used to ‘bind’
1.An architecture body to its entity
declaration
2.A component with an entity
Binding is performed in two ways

• Configuration specification
• Configuration Declaration
Default Binding rules
• If no configuration information is provided
.a default architecture may be found as
follows:
• If the entity name is the same as the
component name ,then this entity is bound
to the component
• The language rules enable a search for
entities with the same names .They may
be found in the working directory
• If there are multiple architectures, the last
compiled architecture will be used.
• Using the default rules, if component
names are the same as the entity names
,we can avoid writing configurations.
• However if no such entity with the same
name is found ,we say the binding is
deferred ,
• which means no information is available
now ,but will be provided later.
Configuration Specification
• It is used to bind component instantiations
to specific entities stored in design
libraries
• The specification appears in the
declarations part of the architecture or
block of components being instantiated.
• Assume there are components X1 ,X2 –
XOR gates , A1 , A2 -AND gates
etc in an adder model.
After the component declarations , write the
configuration specifications.
for X1,X2 :XOR2
use entity WORK.XOR2(BEH);
For A1,A3:AND2
use …
for all:OR1
use…
For others:AND2
Use …
Begin
…port mapping statements…
CONFIGURATION
Declarations

• Self study
• Also –Incremental Binding
SUB PROGRAMS
Functions
• function name can be an operator
• arbitrary number of input parameters
• exactly one return value
• no WAIT statement allowed
• function call <=> VHDL expression
A function call is an expression (like 'a + b')
that can exist within a statement, only.
Procedures
• arbitrary number of parameters of any
possible direction (input/output/inout)
• RETURN statement optional (no return
value!)
• procedure call <=> VHDL statement
• A procedure call, on the other hand, is a
statement (like 'c := a + b;') and therefore
it can be placed inside a process where it
is executed sequentially or inside an
architecture where it acts like any other
concurrent statement.
IMPURE FUNCTIONS
• IMPURE functions can have access to
external objects outside of their scope.
This allows returning different values,
even when called with the same
parameters.
• A good example is the implementation of
a random number generator which returns
a different value each time it is called.
• Actual parameters are the ones used in
the subprogram call and are treated as
constants by default.
• The classes of the formal and actual
parameters must match.
• So it is an error if a parameter is declared
as signal and a variable is used as actual
parameter in the call.
• Parameters of type ' constant ' are an
exception as they match all possible
types.
• Actual parameters (subprogram call)
• must match classes of formal parameter
• class constant matches actual constants,
signals or variables
• So it is an error if a parameter is declared
as signal and a variable is used as actual
parameter in the call. Parameters of type '
constant ' are an exception as they match
all possible types.
FUNCTIONS
• Function parameters are always of mode IN and can
not be declared as variables

• The keyword ' pure ' can be used for "oldstyled"


functions, the keyword ' impure ' declares the new
VHDL'93 function type.
• By default, i.e. if no keyword is given, functions are
declared as PURE. A PURE function does not have
access to a shared variable , because shared variables
are declared in the declarative part of an architecture
and PURE functions do not have access to objects
outside of their scope.
Syntax of a subprogram
specification for a function body

• [pure]impure]function function
name(parameter-list)
return return-type
architecture EXAMPLE of FUNCTIONS is
[(im)pure] function COUNT_ZEROS (A
bit_vector)
return
integer is
variable ZEROS : integer;
begin
ZEROS := 0;
for I in A'range loop
if A(I) = '0' then
ZEROS := ZEROS +1;
end if;
end loop;
return ZEROS;
end COUNT_ZEROS;
How to call a function?
signal WORD: bit_vector(15 downto 0);
signal WORD_0: integer;
signal IS_0: boolean;
begin
WORD_0 <= COUNT_ZEROS(WORD);
process
begin
IS_0 <= true;
if COUNT_ZEROS("01101001") > 0 then
IS_0 <= false;
end if;
wait;
end process;
end EXAMPLE;
example of a function
Library ieee;
Use ieee.std_logic_1164.all;
Entity dff is
Port (D,clk:in std_logic;
Q,QBAR:out std_logic);
End entity dff;
Architecture beh of dff is
Function rising_edge (signal clock:std_logic)
return boolean is
Variable edge: boolean:=false;
Begin
edge:=(clock=‘1’ and clock’event);
Return edge;
end function rising_edge;
Begin
Process
Begin
Wait until (rising_edge(clk);
Q<=D after 4 ns;
QBAR<=nor D after 5 ns;

End process;
End beh;
Learn to write
1)Resolution functions
2)Type conversion functions
Procedures
• Allow decomposition of behaviours into
modules
• Procedures can return zero or more
values using modes in,out or inout
• Syntax is
Procedure procedure-name(parameter list)
Parameters may be constants,variables or
signals
By default –constant if of mode in
Variable if of mode out or inout
Type OP_CODE is
(ADD,SUB.MUL,DIV,LT,LE,EQ);
Procedure ARITH-UNIT is
(A,B:in integer;
OP:in OP-code;
Z:out integer ;
ZCOMP:out boolean) is
Begin
Case OP is
When ADDD=>Z:=A+B;
When SUB=>Z:=A-B;
When MUL=>Z:A*B;
When DIV=>Z:=A/b;
When LT=>ZCOMP:=A/B;
When LE=>ZCOMP:=A<=B;
When EQ=>ZCOMP:=A+B;
End case;
End ARITH_UNIT;
Procedures
architecture EXAMPLE of PROCEDURES is
procedure COUNT_ZEROS
(A: in bit_vector;
signal Q: out integer)
is
variable ZEROS : integer;
begin
ZEROS := 0;
for I in A'range loop
if A(I) = '0' then
ZEROS := ZEROS +1;
end if;
end loop;
Q <= ZEROS;

end COUNT_ZEROS;
signal COUNT: integer;
signal IS_0: boolean;
begin
process
begin
IS_0 <= true;
COUNT_ZEROS("01101001", COUNT);
wait for 0 ns;
if COUNT > 0 then
IS_0 <= false;
end if;
wait;
end process;
end EXAMPLE;
Subprogram Declaration and
Overloading
Subprograms may be declared/defined in
any declaration part
• package
• entity
• architecture
• process
• subprogram
• Subprograms may be declared/defined in any
declarative part of a VHDL object.
• The actual definition of the behaviour may also
be separated from the declaration, which is often
the case when packages are split into package
and package body.
• The usual object visibility rules apply, e.g. a
subprogram which is declared in a package may
be used in all units that reference this package.
• Subprograms that are declared within another
subprogram are available within this "parent"
subprogram, only.
Overloading of subprograms
possible

• identical name
• different parameters
• works with any kind of subprogram
• During compilation/runtime that
subprogram is called whose formal
parameter match the provided actuals