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 Verilog is a hardware description language (HDL)

Verilog HDL is most commonly used in the design, Verilog became IEEE Standard 1364-1995,
commonly referred to as Verilog-95. verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction.
used to model electronic systems.

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General definition

Example module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ denotes XOR assign Carry = A & B; // & denotes AND endmodule

module module_name ( port_list ); port declarations; variable declaration; description of behavior endmodule

Switch Level: Module implemented with switches and interconnects. Lowest level of Abstraction Gate Level: Module implemented in terms of logic gates like (and ,or) and interconnection between gates

Dataflow Level: Module designed by specifying dataflow. The designer is aware of how data flows between hardware registers and how the data is processed in the design Behavioral Level :Module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Very similar to C programming

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Blank space - \b

Tabs - \t
Newline - \n Comments
o One line comments - //

o Multiple line comments - /* */

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 Verilog is case sensitive

All verilog keywords are lower case

o Example:
input //verilog keyword INPUT //a unique name(not a keyword)

Identifiers
o Identifiers are names assigned to modules, signals, variables.. o They must begin with an alphabetic character or underscore o Example:
addbit, sum, a$b, _multi etc

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Sized number
<size><base format> <number>

Base format
o Binary (b or B) o Octal (o or O) o Decimal ( d or D) o Hexa-decimal (h or H)

Exampl e 4b1010 //4-bit binary # 16d255 //16-bit decimal # 9o123 //9-bit Octal # 12habc //12-bit hexadecimal #

Number
o 0 - 9, a - f

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 Value set Nets Registers Vectors Integer, real & time register Arrays Memories Parameters Strings
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0 1 X

Zero, Low, False, Logic Low, Ground, VSS, Negative Assertion

One, High, True, Logic High, Power, VDD, VCC, Positive Assertion

X, Unknown: Occurs at Logical Conflict Which Cannot be Resolved

HiZ, High Impedance, Tri-Stated, Disabled Driver (Unknown)

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Various net types are available for modeling design-specific and

technology-specific functionality
Net Verilog Net Type Function Standard wire, tri Wired OR wor, trior Wired AND wand, triand Capacitive trireg Pullup tri1 Pulldown tri0 Power supply1 Ground supply0 nets that are not explicitly declared default to single-bit nets of type wire module test_fixture ; reg r_in, s_in; rs_ff d1(out, outnot, r_in, s_in); ... endmodule

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 Storage elements
o Variable that can hold value. (not HW Register)

Syntax
reg register_name;

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 Verilog allows constant to be

defined in a module by the keyword parameter

Example
parameter port_id = 5;

Syntax parameter constant_name = value

parameter mem_width = 256

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A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as predefined primitives. These primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition.

 Continuous Assignment
o Implicit Continuous Assignment

Delays
o Regular Assignment Delay

o Implicit Continuous Assignment Delay

o Net Declaration Delay

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// Regular continuous assignment

wire out

assign out = in1 & in2;

//Implicit Continuous Assignment

wire out = in1 & in2;

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assign #10 out = in1 & in2;

in 1

in 2
ou t
10 20 30 60 70 80 85

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Relational

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The left hand side of an assignment must always be a scalar or vector net It cannot be a scalar or vector register. Continuous assignments are always active. The assignment expression is evaluated as soon as one of the right-hand-side operands changes and the value is assigned to the lefthand-side net.

 Structured Procedure
Procedural Assignment Timing Control Delay - Based Timing Control Event - Based Timing control
o Regular event control o Named event control o Event OR control o Regular Delay Control o Intra - assignment Delay control o Zero delay control o Initial Statement o Always Statement

Level sensitive timing control Conditional statements Case statement

o Case keyword o Casex keyword o Casez keyword o While Loop o For Loop o Repeat Loop o Forever Loop

o if - then - else statement

o Blocking Assignment o Nonblocking Assignment

Loop Statement
Sequential Blocks & Parallel
Blocks

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module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; reg s, Cout; always @(x or y or Cin) begin {Cout, s} = x + y + Cin; end endmodule

module dec2to4 (W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(W or En) begin case ({En, W}) 3'b100: Y = 4'b1000; 3'b101: Y = 4'b0100; 3'b110: Y = 4'b0010; 3'b111: Y = 4'b0001; default: Y = 4'b0000; endcase end endmodule

module compare (A, B, AeqB, AgtB, AltB); input [3:0] A, B; output AeqB, AgtB, AltB; reg AeqB, AgtB, AltB; always @(A or B) begin AeqB = 0; AgtB = 0; AltB = 0; if(A == B) AeqB = 1; else if (A > B) AgtB = 1; else AltB = 1; end endmodule

module D_latch(D, Clk, Q); input D, Clk; output Q; reg Q=0; always @(D or Clk) begin if (Clk) Q = D; endmodule

module shift4(R, L, w, Clock, Q); input [3:0] R; input L, w, Clock; output [3:0] Q; reg [3:0] Q; always @(posedge Clock) if (L) Q <= R; else begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= w; end endmodule

module updowncount(R, Clock, L, E, up_down, Q); parameter n=8; input [n-1:0] R; input Clock, L, E, up_down; output [n-1:0] Q; reg [n-1:0] Q; integer direction; always @(posedge Clock) begin if (up_down) direction = -1; else direction = 1; if (L) Q <= R; else if (E) Q <= Q + direction; end endmodule