Power Analysis and Estimation for Digital CMOS Circuits

Jins Davis Alexander Vishwani D. Agrawal

Department of Electrical and Computer Engineering Auburn University, AL 36849 USA
October 18th ,2006 VLSI D&T Seminar 1

Motivation For This Work.

An accurate and efficient power estimation

tool for CMOS circuits. To estimate and separate the different components of power dissipation in a single packaged tool. Knowledge of components of power is useful in design decisions and optimization. Most existing tools estimate the total power or are specific to a particular power component.
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Outline
Existing Power analysis Tools.

Various power components.

Dynamic Power Estimation. Leakage (static) power estimation. Short circuit power estimation. Experimental Results. Future Work. Conclusion.
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Some Power Analysis Tools and Techniques.

PowerMill transistor level simulator for simulation of

current and power from Synopsys. WattWatcher RTL level power estimator from Sente. PowerPlay dynamic power estimator based on logic simulation. Crest pattern independent current estimator. McPower- monte carlo approach to power estimation. Spice Simulators Mentor Graphics tools like Mach PA, ELDO simulator, Silvaco SmartSpice, etc.
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Components of Power Dissipation.

Dynamic Power due to Signal transitions.
Logic power (due to logic transitions). Glitch power (due to glitches).

Short Circuit component.

Static Leakage power (due to leakage currents).

Clock Power

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Power components.
Dynamic power

Leakage power
Short circuit power

Ron

VDD vo(t) CL

vi (t)

R=large Ground

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Dynamic Power
Depends on the switching activity of the gate

and the load capacitance at the output node (switching capacitance). Supply Voltage and clock frequency. Dynamic power = 0.5 i fclk CLi VDD2
All gates i where fclk clock frequency

i activity factor of gate i CLi load capacitance of gate i

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Dynamic power estimation.

Calculation of logic transitions (events) by

means of logic simulation. Event driven simulation algorithm used. Calculate energy dissipated for each event for every gate. Average dynamic power = Total energy/Analysis period.

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Event driven Circular Time Stack

max t=0 1 Event link-list

2
3 4

5
6 7
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Leakage power
Majority of leakage dissipation is due to sub threshold

leakage current.

Ground n+

IG

VDD R

Isub IPT IGIDL

n+

ID
10

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Sub threshold current.

Isub = 0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt}

(1 - exp(-VDS/Vt)
where 0 effective carrier mobility Cox gate oxide capacitance per unit area L: channel length W: gate width Vt = kT/q: thermal voltage n: a technology parameter
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Leakage power estimation.

Leakage power is input vector dependent. Analyze which transistors of the gate are in

ON state or OFF state during steady state analysis. Used BSIM3V3 spice models for calculation of threshold voltage, sub threshold currents for nMOS and pMOS transistors. Weighted time estimation of how long each transistor is in OFF state during the entire simulation period.
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Example of NAND Gate.

VD
D

On Off On

Off Off On

0 1 0

Off On Off On Off

10

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Short Circuit Power.

Short circuit current flows during the time

when both transistors are in ON state. It depends on the rise or fall times of the input waveform. It also depends on the load output capacitance. Decreases for larger output load capacitance. The peak short circuit current occurs at the time when the transistor switching off goes from linear to saturation region.
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Short Circuit Current, isc(t)

V2 Vi(t) VDD - VTp Volt Vo(t)

VTn

isc(t)
Amp

Iscmaxf

0
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t1

t2

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t3

Time (ns)
15

Short circuit current calculation.

R=large vi (t)

VDD

isc(t)
vo(t) CL iC(t) Ground

tr

Ron

tf
16

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Short Circuit Modeling

Ip(T1) = VDD2 Kp[(Vin 1 p )(Vout 1)0.5(Vout 1)2]
Ip(T2) = VDD2 0.5Kp (Vin 1 p )2

where T1 = t2 t1 T2 = t3 t2 Kp = pMOS gain factor. p = Vtp/VDD

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Short Circuit Modeling.

dVout 2 - CL 0.5 Kn (Vin n ) dt 3 t Vout 1 VDDKnt 0 ( n) t0

At t t 2 , Vout Vin p t3 Escf VDDisc (t )dt (t 3 t1) Iscfm axVDD / 2 t1

Reference: Wang, Q. and Vrudhula, S. B. K., "On short circuit power estimation of CMOS inverters," Proc. International Conference on Computer Design (ICCD98), Oct 1998, pp. 70-75.

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Experimental Results (Average Power Dissipation for 1000 Random Vectors)

Circuit Name c432 c499 c880 c1355 c1908 c2670 Dynamic Power (W) 1989.4 2452.5 2720.0 8847.7 17292.3 15531.2 Logic Power (W) 1031.3 1356.7 1632.9 3039.2 5891.2 7373.5 Glitch Power (W) 958.1 1095.8 1087.0 5808.5 11401.0 8157.8 Leakage Power (W) 0.0178 0.0287 0.0396 0.0577 0.1045 0.1024 Short Circuit (pW) 0.47 1.19 0.09 2.84 0.35 1.29 Total Power (W) 1989.42 2452.56 2720.04 8847.71 17292.43 15531.34 CPU Time in secs * 15.3 22.5 37.1 38.7 130.2 98.31

c5315
c7552

44921.8
66953.6

18626.4
25341.3

26295.4
41612.3

0.2263
0.3182

31.26
43.21

44922.10
66953.90

437.2
409.3

* Sun Ultra Workstation

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A Few Observations.
If a gate has a greater fan-out , its dynamic power

dissipation will increase. However the total dynamic dissipation increase will depend on the switching activity of the gate. A gate whose input node has a greater fan-out, will have an increase in short circuit power as the input rise or fall time to that gate will be higher as observed in circuits like c432. A gate with a bigger fan- out can increase short circuit power dissipation only if it causes an event at its fan- out gates. This phenomenon can be seen while comparing circuits c1908 and c2670.
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Experimental Results (Maximum and Minimum Power Components)

Circuit Name Dynamic Power Logic Power in Glitch Power in Leakage Power in W W W in W

Max
c432 c499 c880 c1355 c1908 c2670 c5315 c7552 6657.5 4084.5 6177.3 15765.7 39646.4 32892.6

Min
419.05 594.33 905.99 3388.54 5143.36

Max
1763.95 2197.25 2669.14 4265.47 8554.57

Min
192.79 321.73 666.99

Max
5929.59 3277.46 4535.64

Min
0.00 0.00 0.00 830.86

Max
0.0206 0.0389 0.0480 0.0634 0.1169 0.1075 0.2458 0.3404

Min
0.0144 0.0222 0.0328 0.0485 0.0812 0.0896 0.1856 0.2791
21

1508.90 12411.50

2675.87 32097.70 1437.40

5809.80 10437.50 4331.92 23572.30 1406.87

69993.3 25367.50 24560.70 12607.00 50099.70 8715.63 116104.0 28823.60 32611.60 15398.50 88828.30 9699.80
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Histogram for c7552 (1000 Random Vectors)

1000000 100000 10000

Log ( Power in uW )

1000 100 10 1 0.1 0.01 Dynamic 0.001 0.0001 0.00001

Logic Glitch Leakage Short Circuit Total

Maximum Average

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Investigation of c7552 circuit

The circuit produces a large number of

glitches. Almost 66% of the total events are found to be glitches. Analysis of NAND gate #3718 showed that for a 1 to 0 transition, the gate undergoes 22 extra transitions (glitches) before settling to steady state 0.

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Ongoing Work
Estimation of clock power (power dissipated

in clock trees or clock buffer circuits). Estimation of power in sequential and scan circuits. Spice validation of results at gate level.

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Conclusion
This work discusses the techniques used for

the efficient estimation of power in CMOS circuits. The tool successfully does a gate level logic simulation and separates different power components. Future work involves validation of results through Spice simulation of smaller circuits.

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THANK YOU..

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