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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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ISAs Today
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Processor Classes
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MIPS ISA
100 million MIPS processors manufactured in 2002 MIPS processors used in:
Products from ATI, Broadcom, NEC, Texas Instruments, Toshiba SGI workstations Series2 TiVo Windows CE devices Cisco/Linksys routers Nintendo 64 Sony Playstation 1, PS2 (Emotion), PSP Cable boxes
1984: MIPS Computer Systems R2000 (1985), R3000 (1988), R4000 (64-bit, 1991) SGI acquisition (1992) => MIPS Technologies Transition to licensed IP: MIPS32 and MIPS64 (1999) Heavyweight embedded processor
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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MIPS Microarchitecture
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Tradeoff:
Execution time = instructions per program * cycles per instruction * seconds per cycle
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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Floating-point instructions
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MIPS Registers
32 x 32-bit general purpose integer registers Some have special purposes These are the only registers the programmer can directly use
$0 => constant 0 $1 => $at (reserved for assembler) $2,$3 => $v0,$v1 (expression evaluation and results of a function) $4-$7 => $a0-$a3 (arguments 1-4) $8-$15 => $t0-$t7 (temporary values) Used when evaluating expressions that contain more than two operands (partial solutions) Not preserved across function calls $16-$23 => $s0->$s7 (for local variables, preserved across function calls) $24, $25 => $t8, $t9 (more temps) $26,$27 => $k0, $k1 (reserved for OS kernel) $28 => $gp (pointer to global area) $29 => $sp (stack pointer) $30 => $fp (frame pointer) $31 => $ra (return address, for branch-and-links)
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Design Considerations
Most arithmetic instructions have 3 operands simplifies the hardware
Limits the number of datapaths on the processor
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Arithmetic
Arithmetic (R-type) instructions
add a,b,c sub a,b,c a=b+c a=b-c
C code:
f = (g + h) (i + j)
to
add t0,g,h add t1,i,j sub f,t0,t1
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Registers
f, g, h, i, j in $s0, $s1, $s2, $s3, $s4
To
add $t0,$s1,$s2 add $t1,$s3,$s4 sub $s0,$t0,$t1
Similar instructions:
addu, subu and, or, nor, xor slt, sltu
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Immediate Instructions
Second operand is a 16-bit immediate Signed (-32,768 to 32,767) or unsigned (0 to 65,535) Encoded with I-type addi $s0, $t0, -4
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Example:
Initialize register $t0 with 1234567816 lui $t0, 1234 addi $t1, $0, 5678 or $t0, $t0, $t1
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Shift Instructions
Shift left-logical:
001010012 by 210 => 101001002 Multiply 4110 by 2210 = 16410
Shift right-logical:
001010012 by 210 => 000010102 Divide 4110 by 2210 (round down) = 1010
Shift right-arithmetic
111101012 by 210 => 111111012 Divide -1110 by 2210 (round down) = -310
Amount (0-31) is encoded in SHAMT field for SLL, SRL, SRA Held in a register (rs field) for SLLV, SRLV, SRAV
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Similar instructions:
lh, lhu, lb, lbu sh, sb
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SW $2, 128($3)
I-type memory address instruction Opcode is 101011, rs=00011, rt=00010, imm=0000000010000000 101011 00011 00010 0000000010000000
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Branch Instructions
Branch and jump instructions are required for program control
if-statements loops procedure calls
Unconditional branch
b <label>
Conditional branch
beq, bgez, bgezal, bgtz, blez
and-link variants write address of next instruction into $31 (only if branch is taken) Branch targets are 16-bit immediate offset (offset in words)
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Note:
bltz, bltzal, bgez, bgezal all have opcode 1, func in rt field
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Jump Instructions
Unconditional branch Two types: R-type and J-type
JR $31 JALR $3
R-type jump instruction Opcode is 0s, rs=3, rt=0, rd=31 (by default), func=001001 000000 00011 00000 11111 00000 001001
J 128
J-type pseudodirect jump instruction Opcode is 000010, 26-bit pseudodirect address is 128/4 = 32 000010 00000000000000000000100000
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Immediate addressing
Operand is help as constant (literal) in instruction word Example: ADDI $2, $3, 64
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indirect (offset is 0)
Example: LW $2, 0($4)
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div $2, $3
quotient in lo and reminder in hi div $2, $3, $4 is psuedo (quotient)
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Pseudoinstructions
Some MIPS instructions dont have direct hardware implementations
Ex: abs $2, $3
Resolved to:
bgez $3, pos sub $2, $0, $3 j out pos: add $2, $0, $3 out:
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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If-Statement
if ((a>b)&&(c==d)) e=0; else e=f;
lw $s0,a lw $s1,b bgt $s0,$s1,next0 b nope lw $s0,c lw $s1,d beq $s0,$s1,yup lw $s0,f sw $s0,e b out xor $s0,$s0,$s0 sw $s0,e
next0:
nope:
yup:
out:
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For Loop
for (i=0;i<a;i++) b[i]=i;
lw $s0,a loop0: loop1:
out:
li $s1,0 blt $s1,$s0,loop1 b out sll $s2,S1,2 sw $s1,b($s2) addi $s1,$s1,1 b loop0
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loop0: loop1:
out:
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loop0:
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Complex Loop
for (i=0;i<n;i++) a[i]=b[i]+10;
loop:
test:
li $2,$0 lw $3,n sll $3,$3,2 la $4,a la $5,b j test add $6,$5,$2 lw $7,0($6) addi $7,$7,10 add $6,$4,$2 sw $7,0($6) addi $2,$2,4 blt $2,$3,loop
# # # # #
# # # # # # #
zero out index register (i) load iteration limit multiply by 4 (words) get address of a (assume < 216) get address of b (assume < 216)
compute address of b[i] load b[i] compute b[i]=b[i]+10 compute address of a[i] store into a[i] increment i loop if test succeeds
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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SPIM
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SPIM
ASM file must be edited with text editor Must have main label Must jr $31 at end Use .data and .text to specify sections
Example Code
mystr: .data .asciiz "2887"
main:
loop:
done:
.text addi $s0,$0,0 # addi $s1,$0,0 # addi $s3,$0,10 # lb $s2,mystr($s1) # beqz $s2,done # mul $s0,$s0,$s3 # addi $s2,$s2,-48 # add $s0,$s0,$s2 # addi $s1,$s1,1 # b loop # jr $31 #
initialize $s0 (current value) initialize $s1 (string index) initialize $s3 (value 10) load a character from string exit if it's the NULL character multiply current value by 10 subtract 48 from character (convert to binary) add converted value to current value add one to index loop return to OS
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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Procedures
JAL, JALR, and BGEZAL are designed to call subroutines Return address is linked into $31 ($ra) Need to:
save the return address on a stack to save the return address save the state of the callees registers on a stack have a place for arguments have a place for return value(s)
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Memory Allocation
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The Stack
Stack is designed to hold variable-sized records Stack grows down
Normally the old $fp must be stored in the AR to pop Dont need $fp for fixed-sized ARs
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Callee:
Pushes an activation record onto the stack (decrement $sp) Save the return address ($ra) on the AR Save registers $s0 - $s7 on the AR Perform computation Save return values to $v0 and $v1 Restore $s0 - $s7 Restore $ra JR $ra
Caller:
Reads $v0 and $v1 and continues
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Notes
This convention:
Limited to 4 arguments and 2 return values (bad!) Doesnt save $t0 - $t9, $v0 - $v1, and $a0 - $a3 (bad!) Doesnt allow (variable-size) space on the AR for argument list (saves regs) Doesnt allow (variable-size) space on the AR for callees local variables (bad!) Doesnt allow space on the AR for return value (saves regs) Fixed AR size (good!) Doesnt require the caller to prepare and/or teardown the AR (good!)
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Stack Example
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$sp
$sp+36 $sp
$sn for comp caller $ra for fact $sn for comps caller $ra for comp
$sp+36
lw $ra,32($sp)
add $sp,$sp,36 jr $ra (instruction after jal fact)
$sp+72
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Example
fact: slti beq addi jr L1: addi sw sw addi jal lw lw addi mul jr $t0,$a0,3 $t0,$zero,L1 $v0,$zero,2 $ra $sp,$sp,-8 $ra,4($sp) $a0,0($sp) $a0,$a0,-1 fact $a0,0($sp) $ra,4($sp) $sp,$sp,8 $v0,$a0,$v0 $ra # # # # # # # # # # # # # # test for n < 3 if n >= 1, go to L1 return 2 return allocate space for 2 items save return address save argument set argument to n-1 recurse restore original argument restore the return address pop 2 items return value = n * fact(n-1) -glad we saved $a0 go back to caller
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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O
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I/O
I/O is performed with reserved instructions / memory space Performed by the operating system on behalf of user code Use syscall instruction Call code in $v0 and argument in $a0 Return value in $v0 (or $f0) SPIM services:
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Example
str: .data .asciiz the answer =
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Example Exercise
Copy words from the address in register $a0 to the address in register $a1, counting the number of words in $v0 Stops when 0 is read Do not preserve $a0, $a1, $v0 Terminating word should be copied but not counted addi $v0, $zero, 0 lw $v1, 0($a0) sw $v1, 0($a1) addi $a0, $a0, 4 addi $a1, $a1, 4 beq $v1, $zero, loop
loop:
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Example Exercise
Translate from binary to assembly: AE0B0004 8D080040 Change MIPS:
8 registers 10 bit immediate constants What is the new size of R and I type instructions?
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Example Exercise
field
31-i bits
i-j bits
j bits
Extract the bits from field in register $t0 and place them into the least significant bits of $t1 i = 22, j = 5
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