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Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables Any single function of five variables Any function of four variables together with some functions of six variables Some functions of up to nine variables.
7-2
F(a=1)
LUT 3
F(a,b,c,d,e)
LUT 2
F(a=0)
7-3
F (a, b, c, d , e, f ) mi
i
Minterms
abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef abcdef
7-5
(F4)
Fa
F1 Fa F2
CLB
F3 Fa F4
CLB
a 1
F
CLB
7-6
Decoding Circuits
2-to-4 Decoding circuit
o1 o2
o3 o4
CLB
7-7
Decoding Circuits
10-to-1024 Decoding circuit
x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
F1 F3 F2
CLB
1 1
F4 F5
CLB F1= x4x5x6x7 F2= x0x1x2x3 F3= x8F1F2 F4= x9F3 F5= x9F3
O1023
1 1
O1022
Disadvantages
It needs 1024 CLBs; expensive to implement. It is a two level implementation, resulting large delay.
7-8
ABC B AC
7-9
0 1
0 1
0
A B C Y A
0 1
0 1
0 1
0 1
B C
7-10
b
F(a=1,b=0) F(a=1,b=1) b a a
0 1
If for every variable its complement is also available, any three-input combinational
function can be implemented by a single ACT cell. Some functions with inputs up to eight can be implemented by a single ACT1 cell.
7-11
F1
F2
F3
F4
H1
H2
7-12
0 d f d 1 f e
0 1 0 1 0 1
0 1 0 d f e 0 1 0 1
F8 edf
7-13
Decoding Circuits
4-to-16 Decoding circuit
a
0 0 1 0 1
b
0 0 0 0 1
O0
abcd
c d
a a b b c c d d
Decoder circuits with more than four inputs need multi-level implementation.
7-14
Decoding Circuits
A 10-to-1024 decoder needs
It needs 1070 ACT1 cells
4-to16 2-to-4
x9
cell
level1 level2 level3
7-15
x0 Actel
4-to16
Speed Considerations
For a combinational circuit implemented by a single memory block, its delay depends on neither the function type nor the input transition patterns. Memory For a combinational circuit implemented by mux-based FPGAs, its delay normally depends on the function type and the input transition patterns.
0 1 0 1 0 1
1
0 1
F1=a
a
0 a
1 b
0 1
0 1
The delay of F1 is smaller than that of F2 For F2, d1 is the output delay when inputs switch from F2=ab a=1 and b=1 to a=0 and b=1; d2 is the delay when inputs switch from a=1 and b=1 to a=1 and b=0.
d2 > d1
Assume the delay of OR gate is smaller than that of MUX
7-16
Speed Considerations
To reduce propagation delay, always place signals which arrive late close to the output.
Good
a b c d e CLB
LUT1 LUT2
Bad a b c e d CLB
LUT1 LUT2
Good
0 1
0 1
Bad
0 1
0 1 b a
0 1
0 F2=ab b
Signal a always arrives late
1 a
0 1
F2=ab
7-17
Other Considerations
Always try to balance signal paths to avoid glitches
a b
CLB
CLB
CLB
CLB
b CLB
7-18