Content

Introduction Moores Law Nanotechnology Benefits

Lower Technology Node

Challenges Conclusion Reference

Introduction
Moores Law : number of transistors double in

every two year.

Nanotechnology : manipulation of matter on nano

scale (1 to 100 nm)

Moores Law

Impact
Scaling of parameters All dimensions of transistor

Voltage
Doping levels

Device Parameters
Length (L) ---- 1/s

Width (W) ---- 1/s

Gate oxide thickness (tox) ---- 1/s Supply Voltage (VDD) ---- 1/s

Threshold Voltage (Vtn,Vtp) ---- 1/s

Substrate doping (NA) ---- s

Device Characteristics
Beta (W/L tox ) ---- s

Current (Ids = (VDD Vt)2) ---- 1/s

Resistance (R = VDD/Ids) ---- 1 Gate Capacitance (C = WL/tox) ---- 1/s

Gate Delay (RC) ---- 1/s

Clock Frequency (f) ---- s Dynamic power dissipation (P = CV2f) ---- 1/s2

Chip Area (A) ---- 1/s2

NanoTechnology Used

 Nanotechnology enables the continuation of Moores

Law to minimize the cost of lower technology node

Application of Nanotechnology
Intel launches the Pentium IV processor based on

90 nm technology in 2004 Nano tech. is used in ULSI Manufacturing of SiC device Deposition and structure of new materials----Gate stack by ALD(atomic layer deposition) and MOCVD(metal organic chemical vapour deposition)

 Doping level of SiC device is investigated

Immersion lithography
For joining the memory and processor need

nanotechnology Ion implantation and deposition of material---shallow p-n junction and high energy implantation for CMOS device

Challenges
Main challenges in fabrication Cost of new fab nearly billions of dollars Heating problem with device shrinkage

Testing problem in nano scale so develop new testing

equipments nano probe Transistor on nano tube Nano wires

Lower Technology Node

We are going down from the exiting technology for

satisfying the moores law

Now mentor graphic , samsung and intel developed

14nm technology
Intel introduced Ultrabook laptop in September

2013 but due to defect density issues it will come in 2014

 ITRS-International Technology Roadmap for

Semiconductors
NTRS-National Technology Roadmap for

Semiconductors
Both are the documents developed by the experts of

semiconductor companies

Road map of lower technology node

10 m 1971 3 m 1975 1.5 m 1982 1 m 1985 800 nm 1989 600 nm 1994 350 nm 1995 250 nm 1997 180 nm 1999 130 nm 2002 90 nm 2004 65 nm 2006 45 nm 2008 32 nm 2010 22 nm 2012 14 nm 2014 10 nm est. 2015 7 nm est. 2017 5 nm est. 2019 Half-nodes

Benefits
From nanotech we can reduce fab cost To attain the required feature size

To embed enough memory on a logic chip

To overcome difficulties of scalability

Challenges in Lower Technology node

degradation of device thermal characteristics due to

heating effects failure due to the electrostatic discharge phenomenon stresses due to different rates of thermal expansion of transistor constituents failure of metallic interconnects due to diffusion or flow of atoms along a metal interconnect in the presence of a bias current, known as the electromigration phenomenon.

 Threshold voltages and short-channel effects ---

alternative gate stack materials (high-k dielectrics and metal gates) structures such as dual gate (DG) structures and FinFETs. Heating effect--- Various novel semiconductor thermoelectric coolers and structures such as thermionic and nanowire coolers have been developed For example, thermionic emission current can be used to achieve evaporative cooling by selective emission of hot electrons over a barrier layer from cathode to anode.

 Difficulties of scaling---- Not enough capacitance ,

defect density , soft error rates (error in signalling due to design and construction) Chip level---- chip material decay and release alpha particles System level ---- due to noise in the system bus data change (using low decay rate material we can avoid) leakage current

Leakage Current

Leakage Vs Dynamic Power

Circuit and PD Challenges

Supply Voltage Scaling (for high performance

device) delay increases and cant lower below some limit

If voltage will not scale then increase electric field

(high dielectric or metal gate used)

Scaling of Vt required (FinFET) introduce leakage

 Lithography scaling Used (double patterning ) Wire Interconnect delay(after scaling) it wont get

reduced as compare to cell delay so introduced more delay in chip(nano wire or width increase)
Double patterning reduce the intensity but increased

the chance of scattering

Mask Costs

LOCOS

STI

Conclusion
Cost will be reduced but complexity will increase. Power will be reduced but many leakage

components will increase.

Research work will increased but many new

functionality will increase.

Reference
Nanotechnology journals Intel research papers

IBM Systems and Technology Group paper

Wikipedia

THANK YOU