The Advanced Microcontroller Bus Architecture (AMBA)

AMBA buses

The Advanced High-performance Bus (AHB) The Advanced System Bus (ASB) The Advanced Peripheral Bus (APB)

Bus transfers
The following signal is used to define the transaction timing:
Bus transaction, BTRAN[1:0], indicates whether the next bus cycle will be address-only, sequential or non-sequential. It is enabled by the grant signal and is ahead of the bus cycle to which it refers. The address bus, BA[31:0]. (Not all address lines need be implemented in systems with modest address-space requirements, and in a multiplexed implementation the address is sent down the data bus.) Bus transfer direction, BWRITE. Bus protection signals, BPROT[1:0], which indicate instruction or data fetches and supervisor or user access. The transfer size, BSIZE[1:0], specifies a byte, half-word or word transfer. Bus lock, BLOK, allows a master to retain the bus to complete an atomic read modify write transaction. The data bus, BD[31:0], used to transmit write data and to receive read data. In an implementation with multiplexed address and data, the address is also transmitted down this bus.

A slave unit may give one of the following signal as response:

Bus wait, BWAIT, allows a slave module to insert wait states when it cannot complete the transaction in the current cycle. Bus last, BLAST, allows a slave to terminate a sequential burst to force the bus master to issue a new bus transaction request to continue. Bus error, BERROR, indicates a transaction that cannot be completed. If the master is a processor it should abort the transfer. Bus reset:

Test interface:

 Advanced Peripheral Bus

Advanced High- performance BUS

It supports split transactions, where a slave with a long response latency can free up the bus for other transfers while it prepares its data for transmission. It uses a single clock edge to control all of its operations, aiding synthesis and design verification It uses a centrally multiplexed bus scheme rather than a bidirectional bus with tri state drivers It supports wider data bus configurations of 64 or 128 bits.

The ARM reference peripheral specification Base components

A memory map which allows the base address of the interrupt controller, the counter timers and the reset controller to vary but defines the offsets of the various registers from these base addresses. An interrupt controller with a defined set of functions, including a defined interrupt mechanism for a transmit and receive communications channel. A counter timer with various defined functions. A reset controller with defined boot behavior, power-on reset detection, a 'wait for interrupt' pause mode and an identification register.

Hardware system prototyping tools

Design reuse can reduce the amount of new design work to a small fraction of the total number of gates on the chip. A systematic approach to on-chip interconnect through the use of a bus such as AMBA further reduces the design task. There are still difficult problems to be solved: all of the selected re-usable blocks, which may come from various sources, will really work together correctly? How can the designer be sure that the specified system meets the performance requirements, which often include complex real-time issues? How can the software designers progress their work before the chip is available?

The ARM 'Integrator Rapid SiliconPrototyping

Rapid SiliconPrototyping Thetarget system is modelled in two steps:

1. The selected reference chip is deconfigured' to render those on-chip blocks that are not required in the target system inactive. 2. The blocks required in the target system that are not available on the reference chip are implemented as off-chip extensions.