2cmos

Digital Integrated Circuits Prentice Hall 1995 Devices
Jan M. Rabaey
The Devices
Goal of this chapter
Present intuitive understanding of device operation
Introduction of basic device equations
Introduction of models for manual analysis
Introduction of models for SPICE simulation
Analysis of secondary and deep-sub-micron
effects
Future trends
The Diode
n
p
p
n
B A
SiO
2
Al
A
B
Al
A
B
Cross-section of pn -junction in an IC process
One-dimensional
representation diode symbol
Depletion Region
hole diffusion
electron diffusion
p n
hole drift
electron drift
Charge
Density
Distance
x +
-
Electrical
x
Field
x
Potential
V
W
2
-W
1
0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostatic
potential.
Diode Current
Forward Bias
x
p
n0
n
p0
-W
1
W
2
0
p
n
(
W
2
)
n-region
p-region
L
p
diffusion
Reverse Bias
x
p
n0
n
p0
-W
1
W
2
0
n-region
p-region
diffusion
Diode Types
x
x
p
n0
p
n0
W
n
p
n
(x)
p
n
(x)
W
n
Short-base Diode
Long-base Diode
(standard in semiconductor
devices)
Models for Manual Analysis
V
D
I
D
= I
S
(e
V
D
/|
T
1)
+
V
D
+
V
Don
I
D
(a) Ideal diode model (b) First-order diode model
Junction Capacitance
Diffusion Capacitance
Diode Switching Time
V
src
t = 0
V
1
V
2
V
D
R
src
t = T
I
D
Time
V
D
ON OFF ON
Space charge
Excess charge
Secondary Effects
25.0 15.0 5.0 5.0
V
D
(V)
0.1
I
D

(
A
)
0.1
0
0
Avalanche Breakdown
Diode Model
I
D
R
S
C
D
+
-
V
D
SPICE Parameters
The MOS Transistor
n+ n+
p-substrate
Field-Oxyde
(SiO
2
)
p+ stopper
Polysilicon
Gate Oxyde
Drain
Source
Gate
Bulk Contact
CROSS-SECTION of NMOS Transistor
Cross-Section of CMOS
Technology
MOS transistors
Types and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS
Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
Threshold Voltage: Concept
n+ n+
p-substrate
D S
G
B
V
GS
+
-
Depletion
Region
n-channel
The Threshold Voltage
Current-Voltage Relations
n
+
n
+
p-substrate
D
S
G
B
V
GS
x
L
V(x)
+
V
DS
I
D
MOS transistor and its bias conditions
Current-Voltage Relations
Transistor in Saturation
n+ n+
S
G
V
GS
D
V
DS
> V
GS
- V
T
V
GS
- V
T
+
-
I-V Relation
0.0 1.0 2.0 3.0 4.0 5.0
V
DS
(V)
1
2
I
D

(
m
A
)
0.0 1.0 2.0 3.0
V
GS
(V)
0.010
0.020
\
I
D
V
T
Subthreshold
Current
Triode Saturation
V
GS
= 5V
V
GS
= 3V
V
GS
= 4V
V
GS
= 2V
V
GS
= 1V
(a) I
D
as a function of V
DS
(b) \I
D
as a function of V
GS
(for V
DS
= 5V)
.
S
q
u
a
r
e

D
e
p
e
n
d
e
n
c
e
V
DS
= V
GS
-V
T
NMOS Enhancement Transistor: W = 100 m, L = 20 m
A model for manual analysis
Dynamic Behavior of MOS Transistor
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
The Gate Capacitance
Average Gate Capacitance
Most important regions in digital design: saturation and cut-off
Different distributions of gate capacitance for varying
operating conditions
Diffusion Capacitance
Junction Capacitance
Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest
The Sub-Micron MOS Transistor
Threshold Variations
Parasitic Resistances
Velocity Sauturation and Mobility Degradation
Subthreshold Conduction
Latchup
Threshold Variations
V
T
L
Long-channel threshold
Low V
DS
threshold
Threshold as a function of
the length (for low V
DS
)
Drain-induced barrier lowering
(for low L)
W
L
D
Drain
Drain
contact
Polysilicon gate
D S
G
R
S
R
D
V
GS,eff
Velocity Saturation (1)
E
(
V/
m)
E
sat
= 1.5
u
n

(
c
m
/
s
e
c
)
u
sat
= 10
7
Constant mobility (slope = )
constant velocity
E
t
(
V/
m)
n

(
c
m
2
/
V
s
)
n0
(b) Mobility degradation
(a) Velocity saturation
0
700
250
100
Velocity Saturation (2)
V
DS
(V)
I
D

(
m
A
)
L
i
n
e
a
r

D
e
p
e
n
d
e
n
c
e
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
V
GS
= 1
0.0 1.0 2.0 3.0 4.0 5.0
0.5
1.0
1.5
(a) I
D
as a function of V
DS
(b) I
D
as a function of V
GS
(for V
DS
= 5 V)
.
0.0 1.0 2.0 3.0
V
GS
(V)
0
0.5
I
D

(
m
A
)
Linear Dependence on V
GS
Sub-Threshold Conduction
0.0 1.0 2.0 3.0
V
GS
(V)
10
12
10
10
10
8
10
6
10
4
10
2
l
n
(
I
D
)

(
A
)
Subthreshold exponential region
Linear region
V
T
Latchup
(a) Origin of latchup
(b) Equivalent circuit
V
DD
R
psubs
R
nwell
p-source
n-source
n
+
n
+
p
+
p
+
p
+
n
+
p-substrate
R
psubs
R
nwell
V
DD
n-well
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
MAIN MOS SPICE PARAMETERS
SPICE Parameters for Parasitics
SPICE Transistors Parameters
Fitting level-1 model for manual
analysis
V
GS
= 5 V
V
DS
= 5 V
V
DS
I
D
Long-channel
approximation
Short-channel
I-V curve
Region of
matching
Select k
and
such that best matching is obtained @ V

gs
= V
ds
= V
DD
Technology Evolution
Bipolar Transistor
n-epitaxy
p-substrate
n
+
buried layer
p
+
isolation
n
+
p
+
p
n
+
E B C
p
+
E C
B
n
+
p n
(a) Cross-sectional view.
(b) Idealized transistor structure.
Schematic Symbols and Sign
Conventions
C
E
B
I
B
I
E
I
C
+
+
+
V
BC
V
BE
V
CE
C
E
B
I
B
I
E
I
C
+
+
+
V
BC
V
BE
V
CE
(a) npn (b) pnp
Operations Modes
Forward Active Operation
x
E B C
W
B
Carrier Concentration
Depletion
Regions
0
W
p
e0
p
c0
n
b0
n
b
(0)
Current Components
x
E
B
C
I
C
I
E
I
B
1
2 3
electrons
holes
Reverse Active
x
E
B C
W
B
0 W
p
e0
n
b0
n
b
(0)
p
c0
n
b
(W)
Saturation Mode
x
E
B C
W
B
0 W
p
e0
n
b0
n
b
(0)
p
c0 Q
S
Q
A
n
b
(W)
Cutoff
x
E
B C
W
B
0
W
p
e0
n
b0 n
b
(0)
p
c0
n
b
(W)
Bipolar Transistor Operation
0.0 2.0
V
CE
(V)
0
5
10
15
I
C
(
m
A
)
-3.0 -1.0
V
CE
(V)
-0.5
I
C

(
m
A
)
I
B
=100 A
I
B
=75 A
I
B
=50 A
I
B
=25 A
0
-0.25
I
B
=25 A
I
B
=50 A
I
B
=75 A
I
B
=100 A
Reverse Operation
Forward Operation
Active
Saturation
A Model for Manual Analysis
E
C
B
|
F
I
B
I
B
+
V
BE
I
B
= I
S
(e
V
BE
/|
T
1)
E
C B
|
F
I
B
I
B
+
V
BE(on)
(a) Forward-active (b) Forward-active (simplified)
E
C B
I
B
+
V
BE(sat)
(c) Forward-saturation
+
V
CE(sat)
I
C
<
|
F
I
B
Capacitive Model for Bipolar
Transistor
C
E
B
Q
F
Q
R
C
be
C
bc
S
C
cs
collector-substrate
junction capacitance
base-emitter
base-collector
junction capacitances
base charge
Junction Capacitances
Base Charge - Diffusion Capacitance
Bipolar Transistors - Secondary
Effects
Early Voltage
Beta Variations
Early Voltage
Forward
Active
Saturation
V
A
V
CE
I
C
V
BE3
V
BE2
V
BE1
Parasitic Resistance
n-epitaxy
p-substrate
n
+
buried layer
p
+
isolation
n
+
p
+
p
n
+
E B C
p
+
r
C1
r
C3
r
B
r
C2
r
E
Beta Variations
V
BE
(linear)
ln (I)
I
C
I
B
|
F
High Level Injection
Recombination
I
KF
SPICE models for Bipolar
Main Bipolar Transistor SPICE
Models
Spice Parameters for Parasitics
SPICE Transistor Parameters
Process Variations
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters, such as impurity concentration den-
sities, oxide thicknesses, and diffusion depths. These are caused by non-
uniform conditions during the deposition and/or the diffusion of the
impurities. This introduces variations in the sheet resistances and transis-
tor parameters such as the threshold voltage.
Variations in the dimensions of the devices, mainly resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.
Impact of Device Variations
1.10 1.20 1.30 1.40 1.50 1.60
L
eff
(in mm)
1.50
1.70
1.90
2.10
D
e
l
a
y

(
n
s
e
c
)
0.90 0.80 0.70 0.60 0.50
V
Tp
(V)
1.50
1.70
1.90
2.10
D
e
l
a
y

(
n
s
e
c
)
Delay of Adder circuit as a function of variations in L and V
T

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Digital Integrated Circuits Prentice Hall 1995 Devices

such that best matching is obtained @ V

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