Digital Logic Synthesis for Memristors

Memristor
One type of new emerging nano-devices Memory-Resistor postulated by Leon Chua in 1 !1 "irst physical implementation found by #$ in %&&'

Memristor

Memristor in Digital Logic

(hreshold device
Crossing threshold switches the resistance)conductance of the memristor *nformation is stored in the resistive state

+on-volatile resistance
+o refresh needed

Can switch in nano-seconds with pico-,oule energy -cite #$ paper. #as the potential for high density/ low power logic and memory circuits

$ublished synthesis methods

1. Julien Borghetti, 0regory S1 Snider/ $hilip 21 3ue4es/ 21 2oshua 5ang/ Duncan R1 Stewart/ and R. Stanley Williams. )6memristive)7 switches enable )6stateful)7 logic operations via material implication1 +ature/ 898:'!; <'!9/ 8 %&1&1 A. Chattopadhyay and Z. Rakosi1 Combinational logic synthesis for material implication1 *n =LS* and System-on-Chip -=LS*SoC./ %&11 *>>>)*"*$ 1 th *nternational Conference on/ pages %&& <%&;/ Oct1 %&111 Different assumptions !. "ehtonen and M. "aiho1 Stateful implication logic with memristors1 *n +anoscale ?rchitectures/ %&& 1 +?+O?RC# 6& 1 *>>>)?CM *nternational Symposium on/ pages ;; <;9/ 2uly %&& 1 !. "ehtonen, J.$. %oikonen, and M. "aiho. (wo memristors suffice to compute all boolean functions1 >lectronics Letters/ 89-;.:%; <%8&/ 8 %&1&1 J.$. %oikonen, !. "ehtonen, and M. "aiho. On synthesis of boolean e@pressions for memristive devices using seAuential implication logic1 Computer-?ided Design of *ntegrated Circuits and Systems/ *>>> (ransactions on/ ;1-!.:11% <11;8/ 2uly %&1%1 (.B. Struko), A. Mish*henko, and R. Brayton, Ma@imum (hroughput Logic Synthesis for Stateful Logic: ? Case Study/ preprint. Different assumptions

2.

#. &.

'.

Material +mpli*ation
Conditional logic with multiple interpretations
*f p then A A follows p 111

$arado@ of entailment
?n argument -p-BA. is false/ iff the premise -p. is true and the conclusion -A. is false

p , - p ,

p A pA

*M$L5 Logic
(wo memristors can perform material implication with one pulse < *M$L5 Consider memristors as a switch with two states < Ron/ Roff =oltage drop over $ affects voltage drop over C Result will be stored in C C is input and output memristor

*M$L5 Logic - +otes

>@plains the conditions for C changing its state C is pre-set to D&E -low conductance ) high resistance. =oltage level =FRg determines voltage drop over C Only if $ G D&E =FRg remains low and allows C to change

Material *mplication with Memristors

Material *mplication - +otes

H pulses/ 8 input patterns "irst two pulses to show initial input values of $ and C (hird pulse performs operation -two pulses applied simultaneously to $ and C. "ourth and fifth pulses to read resulting values of $ and C +ote different pulse amplitude during pulse three -=Fset/ =Fcond.

Ihy are we interested in thatJ

CMOS technology scaling is approaching limits Main limitation in modern C$Ks is heat %-terminal device of 1&nm siLe
?llow much higher)denser device integration

Switching between states can be done with pico 2oule

Muilding +?+D from *M$L5

*M$L5 N "?LS> is a computationally complete set of operators % input memristors and one wor4 memristor can build +?+D gate
#aving +?+D we are creating a lin4 to 4nown logic synthesis algorithms

Memristors in digital logic

*M$L5 and "?LS> is a complete set of operations to perform all boolean logic functions ; memristors can perform a +?+D operation
p2 p

p1

(wo-input +?+D needs three pulses

>@amples of implication uses

--ab. &. G -a7Ob7. --ab. -ab.. G -a7Ob7. O ab -& ab. G -ab. -a b. G -a7Ob.

a b a & a b ab

a O b

?ll these circuits assume that value of b already e@ists1 *f it does not e@ist/ we need two inverters -from *M$L5. to create it1

aOb

& a

- a O b. G a P b

b &

a O b G -a P b.

a b a & a b ab

a O b

?ll these circuits assume that value of b already e@ists1 *f it does not e@ist/ we need two inverters -from *M$L5. to create it1

aOb

& a &

- a O b. G a P b

b &

-a P b.

.o/ /e assume that all inputs must 0e *reated /ith State1ul +M%"2 te*hnology 1rom s*rat*h.

.34 5 3R

.34 5 3R
.34 3R /ith t/o inputs
A A x B x

A 0

x B 0 0

A 0 B x

.34

A 0 ? M C

&

.34 is a one WM gate

A
0

26input 3R

B
0 0

X=A+ B

A B
26input 3R is a t/o WM gate
7 7 B

B
7 7

A+B A

.A.( 5 A.(
+?+D N ?+D

+?+D N ?+D .A.( 5 A.(

.A.(
A B

A 0 B x

.A.( 5 A.(
? M C 7 & 7 &

.A.(8a,09
26input .A.( is a one an*illa gate

26input A.( is a t/o an*illa gate

A.(8a,09

Ior4ing -memoriLing. memristor

-ba. Gb7Oa

-c-ba. c. G -c7O -b7Oa.G-bc.7Oa -bcd.7O&

+?+D-b/c/d. %

bcdOyLv

& b c d +?+D-y/L/v. 1

S3%
*mply serves as inverter

4/o Working & Memristors

y L v

-yLv.7 O &
& 1

Reali:ation o1 a Sum o1 positi)e %rodu*ts

? P M7 G -?7 O M.7

+nhi0it gate
% gates
26input +.$+B+4 is a t/o WM gate

? M C

&

A;
7

?7 O M
7

(wo wor4ing bits

? P M7 G -?7 O M.7
B;

.3R <ates

.3R
? M C &

.3R is a t/o WM 0it gate

A
&

B
7 7

8A=B9;

A=B

!>3R <ates

!>3R - ? literals in .A.( - ? +M%"2

? M

7 7 7

A; A
A = B;

B;
7

B = A;

A;B B

!>3R is a three WM gate

?7M O ? M7

A; A B;

S2.4$!S+S W+4$ !>3RS W+4$ .3 "+M+4 3. .@MB!R 3A A.C+""A B+4S

? M

"irst Ior4ing Memristor

A;

7
A
A = B;

B;

7 7 7

Second Ior4ing Memristor

B B = A;

7
A;B

(hird Ior4ing Memristor

?7M O ? M7

C
A;

7
A
A = B;

B;

7 7

7
A;B

B = A;

4his *ir*uit has # /orking memristors and 1' +M%"2 gates

?7M O ? M7 "ourth Ior4ing Memristor

1' +M%"2 gates, # WM

? M

7 7 7

A; A
A = B;

B;
7

B = A;

A;B

?7M O ? M7

M@>

A M C

M@>
7 7 &

A;
7

AB = A;C A

8A;C9;

8AB9;
A B C A;

8A=C;9;

! IM e@pected

M@> is a three an*illa gate

Circuits from reversible gates versus circuits from memristor material implications
Similarities +o fanout *n-gate memory e@ists (i11eren*es +o inverter Different gates

!Bamples o1 typi*al multi6 input gates

8negated9 /hi*h is multi6input

Reali:ation o1 positi)e produ*t

.A.(

? M C

& A A = B A = B = C 8ABC9

8negated9 /hi*h is multi6input

Reali:ation o1 positi)e produ*t

3R

A B C

& A A=B A=B= C

Area and (elay

?rea
*n CMOS: number of gates Memristive logic: number of input O wor4 memristors

Delay
*n CMOS: number of logic levels Memristive logic: number of gates O number of "?LS> operations

3ur @nderstanding o1 "ehtonen;s AlgorithmC Synthesis /ith D6maps

Synthesis with 3maps

21 +M%"2 gates, 2 WM

=ariants of synthesis algorithms

11 "ind all groups in every level -Lehtonen.1 11 "ind only groups corresponding to essential primes and secondary essential primes1 11 "ind minimum SO$ cover of " and SO$ cover of "7 and use groups that correspond to primes from these covers1 11 Kse cost heuristics related to best prime selection1

&

&

&

?ll primes

Secondary essential primes in red

&

&

Secondary essential primes in red

3ernels of $rimary and Secondary essential primes

&

&

?ll essential primes of "7 in red

?ll 4ernels of essential primes of " and "7

& Q Q

&

Ie ta4e 4ernel of the first level -in red.

Ie do not ta4e another 4ernel of the first level because it was not a 4ernel of an essential implicant

& 1 1 1

& & 1

1 Q Q 1

& 1 1 & &

& 1 1 1

& & 1

1 Q Q 1

& 1 1 & &

Ie invert the function

Ie select the group being 4ernel of essential prime of "7

& 1 1 1

& & 1

1 Q Q 1

& 1 1 & &

& 1 1 1

& & 1

Q Q Q Q

& 1 1 & &

Ie select the group being 4ernel of essential prime of "7

Replace with don7t cares

& Q Q Q Q Ie select the group being 4ernel of essential prime of "7 & Q Q Q Q Ie invert the function & 1 1 1

& & 1

1 Q Q 1

& 1 1 & &

Do not select this group

Q Q Q Q

&

& 1

& & 1

Q Q Q 1 Q

& 1 1 & Q Q

& 1 1 1

& & 1

& 1

Q 1 Q 1 Q & Q Q

Q Q

1 1

Ie select the group being 4ernel of essential prime of "7

Ie invert the function

Q Q Q Q Q Q Q

&

Q Q

&

& 1

& & Q

Q Q Q 1 Q

& 1 1 & Q Q

Q Q

Q Q

Q Q

Q Q

Q Q

Ie select the group being 4ernel of essential prime of "7

Ie invert the function

Q Q Q Q Q

Q Q Q Q

&

& 1

Q Q Q

& 1

Q 1 Q 1 Q & Q Q

Q Q

Q Q

Ie select the group being 4ernel of essential prime of "7

Ie invert the function

& 1 Q Q

Q Q Q

& 1

& 1 Q Q

Q Q Q

Q Q Q 1 Q

& 1 1 & Q Q

Q 1 Q 1 Q & Q Q

0roups selected

+umber of levels does not count/ number of pulses counts to cost

; pulses each 8 pulses

% pulses

1 pulse

% pulses

Our method replaces primes from minimal cover with bigger positive groups
11 %1 ;1 81 H1 Ie have more groups than in SO$ Mut groups have less literals Ie have more inverters for layers Ie have no inverters for primes (his tradeoff causes big differences between costs of SO$ and our method for various functions 91 *nteresting research topic

&

&

1 0roups selected

ABC and Automated "ogi* Synthesis

11 Can we use e@isting tools to perform synthesisJ 11 #ow do we integrate memristor logic to these toolsJ 11 ?re the results valid with respect to memristor logic specifics -area/ delay.J

?MC
"rom ?lan Mishchen4o/ KC Mer4eley System for synthesis and verification of binary seAuential logic circuits ?*0 based

(echnology Mapping

*$M$L5 in ?MC
0enlib file (echnology Mapping

?MC Output
Delay is the number of gates O number of memristor initialiLations ?rea is the number of input O wor4 memristors
Cannot be controlled from ?MC

One issue that is special in memristor logic: "anout

.otation
p , - p ,
p A pA p

pA

$arallel "anout
0reen line < previous node will not be overwritten Red line < previous node will be overwritten
Computing n first/ overwrites n' Computing n1& first/ overwrites n!

One node -n! or n'. has to be copied)recomputed

Solving $arallel "anout

Ihat is cheaperJ
Copy or recomputeJ Ihich node is cheaper to recomputeJ

Copying might reAuire one additional wor4 memristor and two pulses Recomputing n' reAuires one pulse Recomputing n! reAuires 8 pulses

Recompute n'

%ost %ro*essing ABC results

"anout reAuires post processing (wo strategies:
Store each value with fanout in an additional memristor -% inverter. Recompute the whole sub-circuit that caused fanout

?rea)Delay trade-off "anout is increasing delay and li4ely the area as well

$ost $rocessing ?MC results

Ben*hmarks
"or more results/ comparison with other SO$ and >SO$ based methods see poster by ?ni4a Raghuvanshi

Ben*hmarks 6 .otes
$ulse Count -?ni4a. Solution for minimum number of wor4 memristors -minimum area. "ollows similar approach as presented with the 4maps $ulse count G delay 0ate count +umber of *M$L5 gates as computed by ?MC Can contain fan-out that has to be post-processed *s not area optimiLed -more than % wor4 memristors. $ulse Count -?MC. $ost processed to avoid harmful fan-out Still not area optimiLed

Con*lusions
11 =ery little published on synthesis with *M$L5 gates 11 =ery little published on synthesis with memristors1 11 ?lthough logic synthesis for memristors may seem similar to standard SO$ or multi-level combinational synthesis/ it is different because of assumption of minimal level number of Ior4ing MemristorsJ Ie created methods to synthesiLe circuits with minimum number of wor4ing memristors Ie created methods to synthesiLe circuits with small but not minimal -;/ 8. wor4ing memristors1

%1 ;1

11

Research Auestion: Dhow important is this assumption for future memristor technologiesJE

Auture /orks
11 SynthesiLe for given fi@ed number of wor4ing memristors %1 Compare various synthesis methods:
11 SO$ %1 >SO$ ;1 (?+( 81 +?+D (ree H1 Mi-decomposition 91 ?shenhurst-Curtis decomposition

;1 ?nalyLe tradeoffs between various methods for various types of functions -symmetric/ unate/ linear/ self-dual/ etc.1

Auture /orks
11 Synthesis of pipelined/ systolic circuits %1 Synthesis of "inite State Machines and seAuential circuits built from bloc4s1 ;1 "uLLy and multiple-valued circuits1 81 >@act synthesis

(he important characteristic of a memristor is shown in the graph in "igure %-b./ where the steep curve shows the low resistance/ as shown by line ?M -the 6on7 state of the memristor. and the flatter curve shows the high resistance -the 6off7 state of the memristor. as shown by line interval CD1 Memristor7s state described by interval ?M can also be called as 6closed7 or in binary state definitions as 617 or 6true71 Similarly/ the state described by line interval CD can also be called 6open7 or in binary state definitions as 6&7 or 6false71 Ihen voltage is increased beyond certain point/ shown as =open/ the state of the memristor changes from closed to open -transition point M to C in the diagram.1 +ow as the voltage is decreased and goes through the Lero point/ the resistance stays the same until the negative voltage e@ceeds =close1 ?t this point the state changes from open to closed -shown by transition from point D to ?.1

*f the voltage remains between =Close and =Open/ then there is no change in the state of the memristor1 (he change from state open to closed and closed to open/ allows memristor to act as a binary switch1 ?nd the fact that the state remains the same when the voltage is between =open and =close provides the important 6memory7 property1 >ven when the voltage is removed/ the state will remain the same/ and is remembered1 Observe that while a transistor is a three-terminal device/ a memristor is only a twoterminal device which simplifies the layout1

"igure 8-b. shows the circuit when the state of memristor $ is 6171

Figure 4: Workings of IMPLY gate using two Memristors. (a) Output when P= ! (") Output when P=#

"igure 8-a. shows the circuit when the state of memristor $ is 6&7 -open.1 $ has a high resistance/ and can be thought of as disconnected/ which implies that the voltage across grounding resistor is Lero1 (his means that the voltage across the memristor C is eAuivalent to = set1 ?s shown in "igure %-b./ =set is greater that =close1 (he high voltage causes the state of C to become 617 regardless of C7s original state -6&7 or 617.1

"igure 8-b. shows the circuit when the state of memristor $ is 6171

+ow $ has a low resistance/ and can be thought of as a wire/ which implies that the voltage across the grounding resistor is now the same as =cond/ the voltage applied at $ input1 (his means that the voltage across C is eAuivalent to =set-=cond1 Refering to "igure %-b. again/ the magnitude of =set-=cond is less than =close/ and is not enough to switch the state of C irrespective of its previous state1 (his means that if C7s state was 6&7/ it will remain 6&71 *f the state was 617/ it will remain 6171

Logic Synthesis for Memristors

"ind all product implicants with positive literals only Replace with donRt care *nvert Repeat until all R1R covered

e@amples
--abc.7O -ab..7 O -bcd. G --a7 O b7 O c7. O ab.7 O bcd G -abc. P -ab.7 O bcd G -abc. P -a7 O b7. O bcd G -b7c. O bcd

c/ >@perimental
direct-current current<voltage switching characteristics -four-probe method.1 (races b<f are offset1 (race a shows a closed-to-open transition/ trace b shows stability and trace c shows an open-to-closed transition1 (races d<f repeat this cycle1 d/ Switch toggling by pulsed voltages -% ms longS =S>(H%H= and =CL>?RH1 =.1 +on-destructive reads at %&1%= test the switch state1

T Figure 2

Illustration of the IMP operation for the four input values of p and q.

T a, IMP is performed by
T T T

two simultaneous voltage pulses, VC and V#$%, applied to swit&hes P and ', respe&tively, to e(e&ute &onditional toggling on swit&h ' depending on the state of swit&h P.

!"

T b, %he truth table for

the operation

q p IMP q.

Figure 2

&, %he blue and red

&urves show the voltages applied and the absolute value of the &urrents read at )un&tions P and ' before and after the IMP voltage pulses. %he measured low* and high*&urrent values reprodu&e the IMP truth table.