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Figure 15.1 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The depletion-load NMOS inverter.
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For pseudo-NMOS logic inverter, only one additional transistor will be needed for each additional gate input.
This structure is similar to depleted-load NMOS but with rather improved characteristics. It also has the advantage of being directly compatible with CMOS circuits.
Figure 15.2 Graphical construction to determine the VTC of the inverter in Fig. 15.1(a).
Figure 15.3 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = Vtp = 1 V, and r = 9.
The larger the value of r, the lower VOL is and the wider the noise margins are. However, the larger r increases the asymmetry in the dynamic response and makes the gate larger for a given (W/L)P.
Ratioed (Pseudo-NMOS) vs. Ratioless (complementary CMOS) logic circuit.
Since kp is r times smaller than kn, tPLH will be r times larger than tPHL. Thus the circuit exhibits an asymmetrical delay performance.
NOR type consumes less area than NAND type. Pseudo-NMOS is suited for applications in which the output remains high most of the time.
Figure 15.4 NOR and NAND gates of the pseudo-NMOS type.
Each of the switches can be implemented either by a single NMOS transistor or by a pair of CMOS transistors connected in CMOS transmission gate configuration. Y=AC
CMOS transmission gate
Figure 15.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate. Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).
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Figure 15.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b) through switch S2.
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The high output voltage (VOH) will not be equal to VDD; rather, it will be lower by Vt, and to make matters worse, the value of Vt can be as high as 1.5 to 2 times Vto (due to body effect). For static consideration, the low value of VOH can cause the Qp of the next CMOS inverter stage to conduct and thus has a finite static current and static power dissipation.
Figure 15.8
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It results in a good 0. Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles in comparison to previous case.
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Process technology. If the Vt can be reduced, the signal-level loss would become less significant. Device with Vt=0 is known as natural device.
Figure 15.10 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q1, to VDD.
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Figure 15.11 The CMOS transmission gate and its circuit symbol.
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14.12 Operation of the transmission gate as a switch in PTL circuits with (a) v I high and (b) v I low. Figure 15.12
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Qn will stop conducting when vo= VDD-Vtn Qp will enter triode region at vo= |Vtp|, but will continue to conduct until C is fully charged and vo= VDD. Qp provides the gate with a good 1. tPLH will be lower than that in the case of single NMOS switch due to additional current available from Qp. Additional Qp, however, adds the value of C.
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Qp will cease conduction when vo falls to |Vtp|. Qn, however, will continue to conduct until C is fully discharged and vo = VOL = 0V.
The transmission gates provide far superior performance than single NMOS switches. The price paid is increased circuit complexity, area and capacitance.
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Figure 15.14 (a) A transmission gate connects the output of a CMOS inverter to the input of another. (b) Equivalent circuit for the purpose of analyzing the Microelectronic Circuits, Sixth Edition
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Figure 15.18 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Precharge phase: Qp ON/ Qe OFF. VY=VDD. Inputs are allowed to change to proper value. Evaluation phase: Qp OFF/ Qe ON. If input combination makes a high output, VOH=VDD. Evaluation phase: Qp OFF/ Qe ON. If input combination makes a low output, the CL will be discharged through PDN and the VY reduces to 0 V.
Figure 15.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.
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Figure 15.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit.
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Figure E 15.10
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Figure 15.23 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).
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Figure 15.25 The basic element of ECL is the differential pair. Here, VR is a reference voltage.
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Figure E15.12
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Figure 15.27 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the ringing that would otherwise corrupt the logic signals. (See Section 15.4.6.)
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OR Voltage transfer characteristics Definition of unity-gain: QA (or QR) is conducting 1% (or 99%) of IE. Assuming the vBE = 0.75V at a emitter current of 1mA for an ECL transistor.
Figure 15.28 Simplified version of the ECL gate for the purpose of finding transfer characteristics.
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15.28 Figure 15.31 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 15.31
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Figure 15.32
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If greater lengths are needed, then transmission lines must be used the reflection is suppressed with proper termination.
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Figure 15.33 Equivalent circuit for determining the temperature coefficient of the reference voltage VR.
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Figure 15.34 Equivalent circuit for determining the temperature coefficient of VOL
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Figure 15.35 Equivalent circuit for determining the temperature coefficient of VOH.
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The applications of ECL include supercomputers, as well as high speed and high frequency communication system.
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Figure 15.37 Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of QN and QP of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices. (c) To reduce the turn-off times of Q1 and Q2, bleeder resistors R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 15.38 Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.
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