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Midterm Presentation Design and Implementation of APB Bridge based on AMBA 4.

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By Manu Ramesh
Reg. No.:120942001
Co Guide: Mr. Shankaranarayana Bhat M Associate Professor Senior scale Department of E&C Manipal Institute of Technology

Guide Dr. D. V. Kamath Professor, Department of E&C Manipal Institute of Technology

Department of Electronics and Communication Engineering, MIT, Manipal

Contents
Introduction Problem Definition Literature Survey Methodology

Algorithm for Coding


Results Conclusion Future work
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Introduction
System On chip (SoC) instead of ICs

Need of OCB
AMBA introduced in 1996

AMBA become the de facto standard for SoC buses.


Objectives of AMBA specification

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Contd..
The AMBA 4.0 specification defines five buses/interfaces
Advanced eXtensible Interface (AXI) Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB) Advanced Trace Bus (ATB)

AXI protocol introduced in AMBA3.0 which is updated in AMBA 4.0 in 2010

APB is a low cost bus protocol and optimized for minimal power
consumption
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Problem Definition
Design and implementation of AMBA AXI4 to APB bridge

Fig no: 1 Signal connections


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Literature Survey
AMBA has 4 versions as follows
1. VER1.0 (ASB & APB) 2. VER 2.0 (AHB) 3. VER 3.0 (AXI, ATB)

4. VER 4.0 (AXI 4,AXI LITE,AXI STREAM (AXI))


In this project, AXI4.0 and APB4.0 are used.

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Contd..
Migration from AHB to AXI
Modern SoC including multi-core clusters, additional DSP,
graphics controllers and other sophisticated peripherals The AHB protocol, even in its multi-layer configuration cannot keep up with the demands of today's SoC AXI having high flexibility

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Contd..
APB
The APB protocol is not pipelined use it to connect to low-bandwidth peripherals

APB revisions

AMBA 2 APB Specification


Basic read and write transfers, and the two APB components the APB bridge and the APB slave

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Contd..
AMBA 3 APB Protocol Specification v1.0
Error response and waiting states added in this version
AMBA APB Protocol Specification v2.0 Strobe signals and protection signals are added in this version in addition to previous

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Methodology
Working of AMBA AXI
Channel Handshake Process of AXI
The source generates the VALID signal to indicate when the data
or control information is available The destination generates the READY signal to indicate that it accepts the data or control information Transfer occurs only when both the VALID and READY signals

are HIGH

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Contd..

Fig no: 2 Handshaking of AXI Department of Electronics and Communication Engineering, MIT, Manipal 11

Contd..
Working of AMBA APB
APB having 3 states
IDLE : This is the initial and the default state of the bus when no
transfer is underway SETUP : The first stage of a transfer is a move to the SETUP state The address, data and control signals are asserted during this phase but may not be stable

ENABLE : The address, data and control signals are stable during
this phase
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Contd..
No Transfer

IDLE PSELX=0 PENABLE=0

SETUP PSELX=1 PENABLE=0

ENABLE PSELX=1 PENABLE=1

FIG NO: 3 AMBA APB state machine Department of Electronics and Communication Engineering, MIT, Manipal 13

Contd..

FIG NO: 4 AXI to APB bridge Department of Electronics and Communication Engineering, MIT, Manipal 14

Contd..
Features of bridge
The Xilinx AXI to APB Bridge is a soft IP core with these features:
AXI interface is based on the AXI4-Lite specification

APB interface is based on the APB3 specification, supports


optional APB4 selection Supports 1:1 (AXI:APB) synchronous clock ratio Connects as a 32-bit slave on 32-bit AXI4-Lite Connects as a 32-bit master on 32-bit APB3/APB4
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Contd..
IDLE

READ_SETUP

WRITE_SETUP

READ_ACCESS

WRITE_ACCESS

READ_WAIT

WRITE_WAIT

FIG NO:3 State transition diagram of proposed bridge Department of Electronics and Communication Engineering, MIT, Manipal 16

Algorithm for Coding


start
no If Aclk in positive edge yes State =4b 0000

yes

If resetn=1 No

no No

If ARVALID=1

yes SATE =4b0001

If AWVALID=1 yes STATE 4b0100

ARREADY=1,PADDR=ARADDR, PWRITE=0,PSEL=1,PENABLE=0

AWREADY=1,PADDR=AWADDR, PWRITE=1,PSEL=1,BAVALID=0,P ENABLE=0

STATE 4b0010

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Contd..
STATE 4b0101,AWREADY=0 ARREADY=0

No

BREADY=1,W VALID=1. yes PENABLE=1,RDATA=PWDAT,PPR OT=AWPROT,PSTRB=WSTRB

RREADY=1 yes

No

PENABLE=1,RDATA=PRDATA,RVALID =1,state=0011

STATE 4b0110 RVALID=0 WRREADY=1,Sta te=0111 RLAST=1 STATE 4b0111 yes WRREADY=0,PENA BLE=0 PENABLE=0,PSEL=0 No

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Contd..

No WLAST=1 Yes BVALID=1,BRESP=0,PSEL=0,P ENABLE=0

FIG NO : 4 FLOW CHART FOR THE PROPOSED BRIDGE

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Result

Write transaction of bridge Department of Electronics and Communication Engineering, MIT, Manipal 20

Contd..

Read transaction of bridge Department of Electronics and Communication Engineering, MIT, Manipal 21

Conclusion
Design and implementation of the AXI4-Lite to APB bridge with following features using Xilinx ISE tool
32-bit AXI slave and APB master interfaces
support up to 16 APB peripherals

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Future work
Design and implementation of multiple AXI masters and multiple slaves

Master 0
AW AR

AXI Interconnect
decoder mux

slave0
AW AR APB Bridge

Master 1
AW AR

slave1
mux

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decoder

AW AR

AXI to APB full module 23

References
1. 2. 3. 4. 5. 6. 7. ARM, AMBA Specification (Rev 2.0). [Online] Available: http://www.arm.com. ARM, AMBA AXI protocol specifications (Version 2), March 2010, [Online] Available: http://www.arm.com. ARM,AMBA 4 ATB Protocol Specification ATBv1.0 and ATBv1.1, March 2010. Chenghai Ma, Zhijun Liu, Xiaoyue Ma, Design and Implementation of APB Bridge based on AMBA 4.0, IEEE transaction ,2011. Priyanka Gandhani, Charu Patel, Moving from AMBA AHB to AXI Bus in SoC Designs: A Comparative Study, Vol-2 No 4 August, 2011. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and synthesis, 2nd ed, Prentice Hall PTR Pub, 2003. Veena Abraham, Soumen Basak, Sabi S, Design of AXI4 Protocol Checker for SoC Integration, International Journal of Emerging Science and Engineering (IJESE, Volume-1, Issue-8, June 2013. V.N.M.Brahmanandam K, Choragudi Monohar, Design of Burst Based Transactions in AMBA-AXI Protocol for SoC Integration, International Journal of Scientific & Engineering Research Volume 3, Issue 7, July-2012 Xilinx ISE synthesis and verification design guide.

8.

9.

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THANK YOU

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QUIRIES

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Introduction
Introduce new concept called OCB(On Chip Bus) in 1996.And later AMBA bus become the de facto standard in SoC bus. Advanced eXtensiable Interface (AXI)4.0.

So now more IPs should communicate with the AMBA4.0


bus. For that Here we are designing an Advanced Peripheral

Bus (APB) bridge.

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right-first-time development technology-independent

modular system design


to minimize the silicon infrastructure required to support efficient on-chip and off-chip communication for both operation and manufacturing test

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Introduction
AXI as a sub-micrometer interconnect. separate address/control and data phases. Interoperability.
AXI supports Out of order processing and multiple outstanding

operations.
separate read and write data channels. burst-based transactions with only start address issued. 1-16 data transfers per burst, Bursts with a transfer size 8-1024 bits.
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Introduction
reduced interface complexity. The APB has unpipelined protocol.

All signal transitions are only related to the rising edge of the
clock. Every transfer takes at least two cycles

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Literature Survey
Reason for this are,
AHB is transfer-oriented. have independent read and write data buses, they cannot operate in full-duplex mode. AXI having 5 channel which independently operate and same trivial of handshaking between source and destination. AXI at interface level uses a special packetized routing protocol called Network-on-Chip.

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Literature Survey
AXI can have multiple outstanding transaction and out of order completion. AHB is a single-channel, shared bus and AXI is multi-channel read/write optimized bus.

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Literature Survey
There are three types of AXI4 interfaces.
AXI4

AXI4-lite
AXI4-stream

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Literature Survey
cause of the AXI having high flexibility.
AXI4 is for memory mapped interfaces and allows burst of up to

256 data transfer cycles with just a single address phase.


AXI4-Lite is a light-weight, single transaction memory mapped interface and is a simple interface to work with both in design and usage. AXI4-Stream removes the requirement for an address phase

altogether and allows unlimited data burst size.

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AXI 4 being the ARMs latest protocol has lots of new features which are not used by most of the peripherals. Thus, the transactions from AXI master has to be converted to APB master transactions for the further processing.

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