ARM7 TDMI INTRODUCTION

The History of ARM

Developed at Acorn Computers Limited,

of Cambridge, England, between 1983 and 1985

ARM follows RISC Mechanism It is used for small size and high performance applications. Simple architecture low power consumption.

ARM7 TDMI Processor

The ARM7TDMI processor is a member of the Advanced

RISC machine family of general purpose 32-bit microprocessor

What does mean ARM7TDMI ? ARM7 - 32-bit Advanced RISC Machine T - Thumb architecture extension

Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb instructions

D - Debug extension M - Enhanced multiplier I - Embedded ICE macrocell extension

ARM7 TDMI Block Diagram

Von Neumann Architecture 3-stage pipeline
fetch, decode, execute

32-bit Data Bus 32-bit Address Bus 37 32-bit registers 32-bit ARM instruction set 16-bit THUMB instruction set

32x8 Multiplier
Barrel Shifter

COMPARISION BETWEEN ARM AND 8051 Microcontroller

1. ARM executes almost all the instruction in only one cycle where as 8051 micro controller takes more than one cycles in almost all the instruction except register transfer. Ex: conditional jump takes 3 cycles for execution ex: DJNZ in 8051 conditional jump takes 1 cycles for execution ex: BNEQ in ARM 2. ARM is a RISC based architecture . 8051 is a CISC but having less number of instruction as compared to ARM which is RISC. 3. ARM is based on load store architecture i.e data processing instruction can not access memory directly , data has to be stored in a register before processing . 8051 can access memory directly . 4. ARM have conditional data processing instruction whereas 8051 does not .

ARM Architecture
Typical RISC architecture:

Large uniform register file

Load/store architecture
Simple addressing modes Uniform and fixed-length instruction fields

Data Sizes and Instruction Sets

When used in relation to the ARM:
Byte means 8 bits Half word means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set
16-bit Thumb Instruction Set

Registers Description
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter 1 dedicated current program status register

5 dedicated saved program status registers

30 general purpose registers 20 registers are hidden from program at different

times(Which are called as Banked Out Registers)

The ARM Register Set

SVC Undef Mode Mode FIQ User IRQ Mode Mode

CurrentVisible Visible Registers Registers Current Current Visible Registers r0

r1 r0 r2 r1 r3 r2 r4 r3 r5 r4 r6 r5

User Mode

Banked Banked Bankedout out outRegisters Registers Registers Banked out Registers
User Abort
r8 r9 r10 r11 r12 r13 (sp) r14 r13 (lr) (sp) r14 (lr)

r7 r6 r8 r7 r9 r8 r10 r9 r11 r10 r12 r11 r13 r12 (sp) (sp) r13 r13 r14 (sp) (lr) r14 (lr) r14 r15 (lr) (pc) r15 (pc) cpsr spsr spsr cpsr

FIQ FIQ
r8 r9 r8 r10 r9 r11 r10 r12 r11 r13 r12 (sp) r14 r13 (lr) (sp) r14 (lr)

IRQ IRQ

SVC SVC

Undef Undef

Abort

r13 (sp) r14 r13 (lr) (sp) r14 (lr)

r13 (sp) r13 (sp) r14 (lr) r14 (lr)

r13 (sp) r14 r13 (lr) (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr spsr

spsr spsr

spsr spsr

spsr spsr

spsr

Operating Modes
Seven operating modes:
User(Non Privileged mode)
Privileged:

System FIQ IRQ Abort

exception modes

Undefined
Supervisor

10

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised Supervisor : Entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations

Un def : used to handle undefined instructions

System : privileged mode using the same registers as user mode

Register Organization Summary

User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ

IRQ

SVC

Undef

Abort

User mode r0-r7, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

Thumb state High registers

r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

r15 (pc)
cpsr spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

Exceptions
Exception Reset Undefined instruction Software interrupt Mode Supervisor Undefined Supervisor Priority 1 6 6 IV Address 0x00000000 0x00000004 0x00000008

Pre fetch Abort

Data Abort Interrupt Fast interrupt

Abort
Abort IRQ FIQ

5
2 4 3

0x0000000C
0x00000010 0x00000018 0x0000001C

Exception types, sorted by Interrupt Vector addresses

13

Progr am Status Register

31 28 27 24 23 16 15 8 7 6 5 4 0

NZCVQ f

U n d e f i n e d s x

I F T mode c

Condition code flags

N = Negative result from ALU

Interrupt Disable bits.

Z = Zero result from ALU

C = ALU operation Carried out V = ALU operation Overflowed

I = 1: Disables the IRQ. F = 1: Disables the FIQ.

T Bit

Sticky Overflow flag - Q flag

Architecture 5TE/J only
Indicates if saturation has occurred

Architecture x T only T = 0: Processor in ARM state T = 1: Processor in Thumb state

Mode bits

J bit
Architecture 5TEJ only

Specify the processor mode

J = 1: Processor in Jazelle state

Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits

Change to ARM state Change to exception mode Disable interrupts (if appropriate) Stores the return address in LR_<mode> Sets PC to vector address

To return, exception handler needs to:

Restore CPSR from SPSR_<mode> Restore PC from LR_<mode>

0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00

FIQ IRQ (Reserved) Data Abort Prefetch Abort

Software Interrupt Undefined Instruction

Reset

Vector Table
Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices

This can only be done in ARM state.

Using a Barrel Shifter:The 2nd Register, optionally with shift operation Operand Shift value can be either be:
Operan d1 Operan d2

5 bit unsigned integer Specified in bottom byte of another register.

Used for multiplication by

constant
Barrel Shifter

Immediate value 8 bit number, with a range of 0-

255.

Rotated right through even number of positions

ALU

Allows increased range of 32-bit

constants to be loaded directly into registers

Result

Pipeline Organization
3-stage pipeline: Fetch Decode - Execute Three-cycle latency,

one instruction per cycle throughput

i n s t r u c t i o n

Fetch
i+1

Decode Fetch
i+2

Execute Decode Fetch Execute Decode Execute

cycle

t+1

t+2

t+3

t+4

17

AMBA bus architecture

The ARM7 family processors are designed for use

with the Advanced Microcontroller Bus Architecture (AMBA).

o The AMBA specification defines two buses: Advanced High-performance Bus (AHB) Advanced Peripheral Bus (APB).

An Example AMBA System

High Performance ARM processor High Bandwidth External Memory Interface High-bandwidth on-chip RAM

APB

UART Timer

AHB

APB Bridge Keypad PIO

Low Power Non-pipelined Simple Interface

DMA Bus Master

High Performance Pipelined Burst Support Multiple Bus Masters

Queries