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VLSI Design

MOS Transistor Theory


Silicon Semiconductors
Modern electronic chips are built mostly on silicon substrates
Silicon is a Group IV semiconducting material
crystal lattice: covalent bonds hold each atom to four neighbors
Si Si Si
Si Si Si
Si Si Si
Modern transistors are few microns wide and approximately
0.1 micron or less in length
Human hair is 80-90 microns in diameter
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the 20s in USA and Germany
Not widely used until the 60s or 70s
MOS Transistors
Four terminal device: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO
2
(oxide) is a good insulator (separates the gate from the body
Called metaloxidesemiconductor (MOS) capacitor, even though gate is
mostly made of poly-crystalline silicon (polysilicon)
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
NMOS
PMOS
Transistor structure
n-type transistor:
NMOS Operation
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S
NMOS Operation Cont.
When the gate is at a high voltage: Positive charge on gate
of MOS capacitor
Negative charge is attracted to body under the gate
Inverts a channel under gate to n-type (N-channel, hence
called the NMOS) if the gate voltage is above a threshold voltage
(VT)
Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
PMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (V
DD
)
Drain is at a lower voltage than the Source
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
CMOS Fabrication
CMOS transistors are fabricated on silicon
wafer
Wafers diameters (200-300 mm)
Lithography process similar to printing press
On each step, different materials are
deposited, or patterned or etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires to make an n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
Use heavily doped well and substrate contacts/taps (or
ties)
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap well tap
n+ p+
Inverter Mask Set
Top view
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
In
In reality >40 masks
may be needed
Fabrication Steps
Start with blank wafer (typically p-type where NMOS is created)
Build inverter from the bottom up
First step will be to form the n-well (where PMOS would reside)
Cover wafer with protective layer of SiO
2
(oxide)
Remove oxide layer where n-well should be built
Implant or diffuse n dopants into exposed wafer to form n-well
Strip off SiO
2
p substrate
Oxidation
Grow SiO
2
on top of Si wafer
900 1200 C with H
2
O or O
2
in oxidation
furnace
p substrate
SiO
2
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Property changes where exposed to light

Two types of photoresists (positive or negative)
Positive resists can be removed if exposed to UV light
Negative resists cannot be removed if exposed to UV light


_

p substrate
SiO
2
Photoresist
Lithography
Expose photoresist to Ultra-violate (UV)
light through the n-well mask
Strip off exposed photoresist with
chemicals
p substrate
SiO
2
Photoresist
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
N-well pattern is transferred from the mask to
silicon-di-oxide surface; creates an opening to the
silicon surface

p substrate
SiO
2
Photoresist
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
p substrate
SiO
2
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic-rich gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO
2
, only enter exposed Si
SiO
2
shields (or masks) areas which remain p-type

n well
SiO
2
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
Polysilicon
(self-aligned gate technology)
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH
4
)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

Thin gate oxide
Polysilicon
p substrate
n well
Polysilicon Patterning
Use same lithography process discussed earlier to
pattern polysilicon

Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Self-Aligned Process
Use gate-oxide/polysilicon and masking to
expose where n+ dopants should be
diffused or implanted
N-diffusion forms nMOS source, drain, and
n-well contact

p substrate
n well
N-diffusion/implantation
Pattern oxide and form n+ regions
Self-aligned process where gate blocks n-dopants
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing
p substrate
n well
n+ Diffusion
N-diffusion/implantation cont.
Historically dopants were diffused
Usually high energy ion-implantation used
today
But n+ regions are still called diffusion

n well
p substrate
n+ n+ n+
N-diffusion cont.
Strip off oxide to complete patterning step
n well
p substrate
n+ n+ n+
P-Diffusion/implantation
Similar set of steps form p+ diffusion
regions for PMOS source and drain and
substrate contact
p+ Diffusion
p substrate
n well
n+ n+ n+ p+ p+ p+
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide (FO)
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Contact
Metalization
Sputter on aluminum over whole wafer
Copper is used in newer technology
Pattern to remove excess metal, leaving wires

p substrate
Metal
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Metal
Derivation of transistor characteristics
MOSFET gate as capacitor
Basic structure of gate is parallel-plate capacitor:
gate
substrate
SiO
2
x
ox
V
g
+
-
+ + + + + + + + + + + +
- - - - - - - - - - - -
inversion
MOS as a parallel plate capacitance
Formula for parallel plate capacitance/unit area:
C
ox
= c
ox
/ t
ox
,
where t
ox
is the thickness of the SO
2
in cm, and
c
ox
is its permittivity:
c
ox
= 3.46 x 10
-13
F/cm

Gate to substrate capacitance helps determine the
characteristics of a channel which forms an inversion region
(region devoid of dopant carriers in the substrate) between
the source and drain of a MOS transistor. In particular, it plays
a critical role in the determination of the threshold voltage of
a MOS transistor.
Threshold voltage
The threshold voltage, V
t0
, when the source to substrate voltage is 0.
V
t0
= V
fb
+ |
s
+ Q
b
/C
ox
+ V
II

Components of V
t0
are:
V
fb
= flatband voltage between gate and substrate, i.e., the work function
difference between gate and substrate. The work function is the energy required
to remove an electron from the Fermi energy to the vacuum level.
|
s
is the surface potential which is equal to twice the Fermi potential
where n
i
is the intrinsic carrier (electron or hole) concentration of the substrate,
kT/q is the thermal voltage, and N
a
is the hole concentration in the substrate.
Q
b
/C
ox
is the voltage across the capacitor, where , q is the charge
of an electron, c
si
is the permittivity of silicon,
V
II
is the voltage adjustment = qD
I
/C
ox
, where D
I
is the ion implantation
concentration (body effect)

Q
b
= 2qc
si
N
a
|
s

=
2kT
q
ln
N
a
n
i
Threshold voltage
The flat-band voltage between gate and substrate depends on the difference in
the work function between gate and substrate (u
gs
) and on fixed surface charge
(Q
f
):




assuming that the gate is doped with n-type carriers with the concentration of N
dp

When the source to substrate voltage is not 0 then the threshold voltage is
shifted by a differential voltage, called the body effect:

V
fb
= u
gs

Q
f
C
ox
u
gs
=
kT
q
ln
N
a
N
dp
n
i
2

AV
t
=
n
( |
s
+V
sb
|
s
)

n
=
2qc
si
N
a
C
ox
Body effect
Reorganize threshold voltage equation:
V
t
= V
t0
+ AV
t
Threshold voltage is a function of
source/substrate voltage V
sb
.
Body effect is the coefficient for the V
sb

dependence factor.
Channel length modulation length
parameter
o describes small dependence of drain current on V
ds

in saturation.
Factor is measured empirically.
New drain current equation:
I
d
= 0.5k (W/L)(V
gs
- V
t
)
2
(l - o V
ds
)
Equation has a discontinuity between linear and
saturation regions---small enough to be ignored.
Note: I use o instead of to avoid confusion with
channel parameter .
Gate voltage and the channel
gate
drain source
current
I
d
V
ds
< V
gs
- V
t

V
gs
> V
ds
+ V
t
gate
drain source
current
I
d
gate
drain source
I
d
V
ds
= V
gs
- V
t

V
gs
= V
ds
+ V
t

V
ds
> V
gs
- V
t

V
gs
< V
ds
+ V
t
Linear region
Saturation region
Inversion layer
current
Pinch off
dI
d
/dV
ds
decreases
Channel transconductance decreases
Inversion layer shrinks
Leakage and subthreshold current
A variety of leakage currents draw current
away from the main logic path.
The sub-threshold current is one particularly
important type of leakage current.
(When the gate voltage is just below the
threshold voltage, the point of weak-
inversion)
Types of leakage current.
Weak inversion current (sub-threshold current).
Punch-through currents. (When the drain to source voltage gets
to be too high, the source and drain regions may be shorted.)
Gate oxide tunneling-- Hot carriers
(For short channels, electrons may accumulate into the gate oxide, leading to
changes in threshold conditions.)
Reverse-biased pn junctions
Drain-induced barrier lowering (Shift in threshold level to
increase in drain voltage-- higher current flow near cut-off when the drain
voltage increases)
Gate-induced drain leakage (As gate oxide layer becomes very
thin, channel current may leak into the gate-- non-ideal capacitor)

Subthreshold current
Subthreshold current:




I
DS
=
W
L
' I e
q(V
GS
V
T
) nkT
1 e
qV
DS
kT
( )
2 '
2 2
2
t
SB F
A S
V
N q
I |
|
c

+
=
SB F
V
n
+
+ =
|

2 2
1
I
DS
=
W
L
' I e
q(V
GS
V
T
) nkT
when V
ds
>> q/kT

log
10
I
DS
= log
10
W
L
' I
|
\

|
.
|
+
q
kT
V
GS
V
T
n
log
10
e

1
S
=
1
n
q
kTln(10)
S is called the sub-threshhold swing;
smaller values of S are desirable