Computer Arithmetic

CS1251 Computer Organization Carl Hamacher

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Full Adder
Ai Bi Ci Ci+1 Si

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

0 1 1 0 1 0 0 1

Si Ai Bi Ci Ci 1 AiBi AiCi BiCi

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Ripple-Carry Adder
A3 B3 A2 B2 A1 B1 A0 B0

A C4 Cout S

B Cin C3

A Cout S

B Cin C2

A Cout S

B Cin C1

A Cout S

B Cin C0

S3

S2

S1

S0

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Subtraction
A B A B 1
SEL 0 0 1 1 B 0 1 0 1 XOR 0 1 1 0

B SEL

B
B

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Adder / Subtractor
A1 B1 A0 B0 SEL

B
Cin

A
Cout

B
Cin

Cout

Cout

FA1
S

FA0
S

R1

R0

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Condition Code Flags

N (negative)

Set to 1 if result is negative

N = R15

Z (zero)

Set to 1 if result is zero

Z = not (R15 or R14 or or R0)

V (overflow)

Set to 1 if arithmetic overflow occurs

V = (A15 and B15 and not S15) or (not A15 and not B15 and S15)

C (carry)

Set to 1 if a carry-out results

C = C16 Note: otherwise cleared to 0

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Carry-Lookahead Addition
si x i y i c i c i 1 x i y i x ic i y ic i

ci 1 xi yi ( xi yi )ci

c i 1 Gi Pic i Gi x i y i Pi x i y i
Generate (both 1) Propagate (either 1)

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Bit-stage Cell
xi yi

ci B cell Gi P i si

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Carry-Lookahead Addition
ci 1 Gi Pici ci Gi1 Pi1ci1 ci 1 Gi PiGi1 Pi Pi1ci1
ci 1 Gi Pi Gi 1 Pi Pi 1Gi 2 Pi Pi 1 P 1G0 P iP i 1 P 0 c0

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4-bit Carry-Lookahead Adder

c1 G0 P0c0 c2 G1 P 1G0 P 1P 0c 0 c3 G2 P2G1 P2P 1G0 P 2P 1P 0c 0 c4 G3 P3G2 P3P2G1 P3P2P 1G0 P 3P 2P 1P 0c0
Limited by fan-in

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4-bit Carry-Lookahead Adder

x3 y3 c3 x2 y2 c2 x1 y1 c1 x0 y0

c4

B cell

B cell

B cell

B cell

c0

s3 G3 P3 G2

s2 P2 G1

s1 P1 G0

s0 P0

Carry-lookahead logic

G0I

P0I

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Propagation Delay (4-bits)

Ripple-Carry Adder

2n gate delays = 8 gate delays

4 gate delays

Carry-Lookahead Adder

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Higher-Level Functions
P0I P3 P2 P1P0
I G0 G3 P3G2 P3 P2G1 P3P2 P 1G0

I c 4 G0 P0I c 0
I I c8 G1I P G 1 0

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16-bit Carry-Lookahead Adder

x15-12 y15-12 4-bit adder s15-12 G3I P3I G2I c12 x11-8 y11-8 4-bit adder s11-8 P2I G1I c8 x7-4 y7-4 4-bit adder s7-4 P1I G0I c4 x3-0 y3-0

c16

4-bit adder s3-0 P0I

c0

Carry-lookahead logic

G0II

P0II

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Propagation Delay (16-bit)

Ripple-Carry Adder

2n gate delays = 32 gate delays

10 gate delays 8 gate delays

Cascading (4) 4-bit Carry-Lookahead Adders

Carry-Lookahead Adder (w/higher level fns)

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Propagation Delay (32-bit)

Ripple-Carry Adder

2n gate delays = 64 gate delays

18 gate delays 10 gate delays 64-bit adder => 12 gate delays
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Cascading (8) 4-bit Carry-Lookahead Adders

Carry-Lookahead Adder (w/higher level fns)

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Multiplication (Unsigned)
A x B P

A3 B3

A2 B2

A1 B1

A0 B0

A3B0 A2B0 A1B0 A0B0 A3B1 A2B1 A1B1 A0B1

+ P7

A3B2 A2B2 A1B2 A0B2 A3B3 A2B3 A1B3 A0B3

P6 P5 P4 P3 P2 P1 P0

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Multiplication Example
7 x 5 35 0 1 1 1 x 0 1 0 1 0 1 1 1 0 0 0 0 +

0 1 1 1 0 0 0 0
0 0 1 0 0 0 1 1

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Array Multiplier
A x B P

A3 B3

A2 B2

A1 B1

A0 B0

4-bit Adders

A3B0 A2B0 A1B0 A0B0 A3B1 A2B1 A1B1 A0B1 A3B2 A2B2 A1B2 A0B2

+ P7
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A3B3 A2B3 A1B3 A0B3

P6 P5 P4 P3 P2 P1 P0
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See also, Fig 6.6

Hardware Requirements
n-bit Multiplication (2n-bit Product)

n2 And Gates (n-1) x n-bit Adders 256 And Gates 15 x 16-bit Adders 1024 And Gates 31 x 32-bit Adders
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16-bit Multiplication

32-bit Multiplication

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Sequential Multiplier
Shift Right

B Register
B0

A Register
8

Shift Left

8-bit Adder
8

Product Register
8

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Alternate Sequential Multiplier

MULTIPLIER

Control Signals
AR_Op QR_Op MR_Op Clr_Bar Sel Halt

CF
Cout A S Cin B

AR

QR

MUX

Sel

MR
MULTIPLICAND

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Shift Register

OP

Mode
SR CLK

00 Hold
01 Clear 10 Shift Right 11 Load

Op

SR
Q

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Multiplication Example
MR 0111 CF 0 AR QR Function Initialize Cycle 0 0000 0101

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Multiplication Example
MR 0111 CF 0 0 AR QR Function Initialize Add MR Cycle 0 0000 0101 0111 0101

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0011 1010

Add 0

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0
0

0011 1010
0001 1101

Add 0
Shift

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0
0 0

0011 1010
0001 1101 1000 1101

Add 0
Shift Add MR

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0
0 0

0011 1010
0001 1101 1000 1101

Add 0
Shift Add MR

0100 0110

Shift

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0
0 0

0011 1010
0001 1101 1000 1101

Add 0
Shift Add MR

0
0

0100 0110
0100 0110

Shift
Add 0

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Multiplication Example
MR 0111 CF 0 0 0 AR QR Function Initialize Add MR Shift Cycle 0 0000 0101 0111 0101 0011 1010

0
0 0

0011 1010
0001 1101 1000 1101

Add 0
Shift Add MR

0
0 0
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0100 0110
0100 0110 0010 0011

Shift
Add 0 Shift

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Questions?

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