CSE477 VLSI Digital Circuits Fall 2002 Lecture 17: Static Sequential Circuits

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

CSE477 L17 Static Sequential Logic.1 Irwin&Vijay, PSU, 2002

Review: How to Choose a Logic Style

Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing
4-input NAND
Style # Trans Comp Static 8 CPL* 12 + 2 domino 6+2 DCVSL* 10 * Dual Rail Ease 1 2 4 3 Ratioed? Delay Power no 3 1 no 4 3 no 2 2 + clk yes 1 4

Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.
Irwin&Vijay, PSU, 2002

CSE477 L17 Static Sequential Logic.2

A time was probably coming when components would operate so quickly that the distance that signals had to travel would intimately affect the speed of most commercial computers. Then miniaturization and speed would become more nearly synonymous. The Soul of a New Machine, Kidder, pg. 160

CSE477 L17 Static Sequential Logic.3

Irwin&Vijay, PSU, 2002

Sequential Logic

Inputs Combinational Logic Current State

Outputs

Next State

clock
CSE477 L17 Static Sequential Logic.4 Irwin&Vijay, PSU, 2002

Timing Metrics

clock

clock
tsu thold

time

In

data stable tc-q

time
output stable

Out

output stable

time
CSE477 L17 Static Sequential Logic.5 Irwin&Vijay, PSU, 2002

System Timing Constraints

Inputs Combinational Logic Current State Next State T (clock period) clock tcdreg + tcdlogic thold
CSE477 L17 Static Sequential Logic.6

Outputs

T tc-q + tplogic + tsu

Irwin&Vijay, PSU, 2002

Static vs Dynamic Storage

Static storage

preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating)

Dynamic storage

store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power

CSE477 L17 Static Sequential Logic.7

Irwin&Vijay, PSU, 2002

Latches vs Flipflops

Latches

level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode

Flipflops (edge-triggered)

edge sensitive circuits that sample the inputs on a clock transition

- positive edge-triggered: 0 1 - negative edge-triggered: 1 0

built using latches (e.g., master-slave flipflops)

CSE477 L17 Static Sequential Logic.8

Irwin&Vijay, PSU, 2002

Review: The Regenerative Property

Vi1 Vo1 Vi2 Vo2

cascaded inverters
A C

B
Vi1 = Vo2

If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.

CSE477 L17 Static Sequential Logic.9

Irwin&Vijay, PSU, 2002

Bistable Circuits

The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)

Vi1 Vi2

Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1

done by applying a trigger pulse at Vi1 or Vi2 the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)

Two approaches used

cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs)
Irwin&Vijay, PSU, 2002

CSE477 L17 Static Sequential Logic.10

Review (from CSE 271): SR Latch

S
S !Q 0 1 0 R Q 1

R
0 0 1 1

Q
Q 1 0 0

!Q
!Q 0 1 0 memory set reset disallowed

CSE477 L17 Static Sequential Logic.11

Irwin&Vijay, PSU, 2002

Review (from CSE 271): Clocked D Latch

D !Q

clock transparent mode clock

clock hold mode

CSE477 L17 Static Sequential Logic.12 Irwin&Vijay, PSU, 2002

MUX Based Latches

Change the stored value by cutting the feedback loop

feedback feedback

1 Q D 0 clk Negative Latch Q = clk & Q | !clk & D transparent when the clock is low
CSE477 L17 Static Sequential Logic.13

0 Q D 1 clk Positive Latch

Q = !clk & Q | clk & D

transparent when the clock is high
Irwin&Vijay, PSU, 2002

TG MUX Based Latch Implementation

clk Q !clk D clk clk D Q input sampled (transparent mode)

!clk

clk
CSE477 L17 Static Sequential Logic.14

feedback (hold mode)

Irwin&Vijay, PSU, 2002

PT MUX Based Latch Implementation

clk !Q Q

input sampled (transparent mode) !clk

Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance

CSE477 L17 Static Sequential Logic.15

clk

!clk

feedback (hold mode)

Irwin&Vijay, PSU, 2002

Latch Race Problem

B B B

clk

clk

Which value of B is stored?

Two-sided clock constraint T tc-q + tplogic + tsu Thigh tc-q + tcdlogic

CSE477 L17 Static Sequential Logic.16 Irwin&Vijay, PSU, 2002

Master Slave Based ET Flipflop

D
0 1 D 0 clk QM 1 clk Slave clk D QM Q
Irwin&Vijay, PSU, 2002

clock

Master
clk = 0 transparent clk = 01 hold

hold

transparent

CSE477 L17 Static Sequential Logic.17

MS ET Implementation
Master Slave

I2

T2

I3 QM

I5

T4

I6

D clk

I1

T1

I4

T3

master transparent slave hold clk !clk

CSE477 L17 Static Sequential Logic.19

master hold slave transparent

Irwin&Vijay, PSU, 2002

MS ET Timing Properties

Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0 Set-up time - time before rising edge of clk that D must be valid
3 * tpd_inv + tpd_tx

Propagation delay - time for QM to reach Q

tpd_inv + tpd_tx

Hold time - time D must be stable after rising edge of clk

zero

CSE477 L17 Static Sequential Logic.21

Irwin&Vijay, PSU, 2002

Set-up Time Simulation

3 2.5 2 1.5

Q QM

tsetup = 0.21 ns

Volts

1 0.5 0

clk
I2 out works correctly

-0.5 0 0.2 0.4 0.6 0.8 1

Time (ns)
CSE477 L17 Static Sequential Logic.22 Irwin&Vijay, PSU, 2002

Set-up Time Simulation

3 2.5 2

I2 out

tsetup = 0.20 ns

Volts

1.5 1 0.5 0 -0.5 0 0.2 0.4 0.6 0.8 1

clk
QM fails Time (ns)

CSE477 L17 Static Sequential Logic.23

Irwin&Vijay, PSU, 2002

Propagation Delay Simulation

3 2.5 2 1.5

tc-q(LH) = 160 psec

Volts

1 0.5 0 -0.5 0

tc-q(LH)

tc-q(HL)

tc-q(HL) = 180 psec

0.5

1.5

2.5

Time (ns)
CSE477 L17 Static Sequential Logic.24 Irwin&Vijay, PSU, 2002

Reduced Load MS ET FF

Clock load per register is important since it directly impacts the power dissipation of the clock network.

Can reduce the clock load (at the cost of robustness) by making the circuit ratioed
clk I1 D T
1

!clk I3

QM
I2

T
2

Q I4

!clk

clk reverse conduction

to switch the state of the master, T1 must be sized to overpower I2 to avoid reverse conduction, I4 must be weaker than I1
Irwin&Vijay, PSU, 2002

CSE477 L17 Static Sequential Logic.25

Non-Ideal Clocks

clk
!clk

clk
!clk

Ideal clocks

Non-ideal clocks clock skew

1-1 overlap
0-0 overlap

CSE477 L17 Static Sequential Logic.26

Irwin&Vijay, PSU, 2002

Example of Clock Skew Problems

clk D P1 A I1 P2 I2 B X !clk P3 I3 P4 clk I4 Q !Q

!clk

Race condition direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap)

Undefined state both B and D are driving A when clk and !clk are both high
Dynamic storage when clk and !clk are both low (0-0 overlap)
CSE477 L17 Static Sequential Logic.27 Irwin&Vijay, PSU, 2002

Pseudostatic Two-Phase ET FF
clk1 D P1 A I1 P2 clk2 master transparent slave hold I2 B X clk2 P3 I3 P4 I4 Q !Q

clk1
dynamic storage

clk1
tnon_overlap clk2
CSE477 L17 Static Sequential Logic.28

master hold slave transparent

Irwin&Vijay, PSU, 2002

Two Phase Clock Generator

A clk clk1

clk2

clk A B clk1 clk2

CSE477 L17 Static Sequential Logic.29 Irwin&Vijay, PSU, 2002

Power PC Flipflop
clk !clk

1D

0 1

1 0

1 0

Q 0 1

!clk

clk

master transparent slave hold clk !clk

CSE477 L17 Static Sequential Logic.31

master hold slave transparent

Irwin&Vijay, PSU, 2002

Ratioed CMOS Clocked SR Latch

off on
M2 M4

on off

1 0 0 1 clk 0 S

Q !Q
off->on
M6

1 0

off->on
M8
M7

clk 0 1
R1

on off
M5 off

M1

off on on

M3

CSE477 L17 Static Sequential Logic.33

Irwin&Vijay, PSU, 2002

Sizing Issues
2

1.5

so W/L5and6 > 3
!Q (Volts)
1

0.5

0 2 2.5 3 3.5 4

W/L5and6

W/L2and4 = 1.5m/0.25 m W/L1and3 = 0.5m/0.25 m

CSE477 L17 Static Sequential Logic.34

Irwin&Vijay, PSU, 2002

Transient Response
3

SET Q & !Q (Volts)

2

!Q
1

Q tc-Q

tc-!Q

0 0.9 1 1.1 1.2 1.3 1.4 1.5

Time (ns)

CSE477 L17 Static Sequential Logic.35

Irwin&Vijay, PSU, 2002

6 Transistor CMOS SR Latch

clk R clk S

clk
R
M5

clk
M2 M4

!Q
M1 M3

M6

CSE477 L17 Static Sequential Logic.36

Irwin&Vijay, PSU, 2002

Next Lecture and Reminders

Next lecture

Dynamic sequential circuits

- Reading assignment Rabaey, et al, 7.3, 7.7

Reminders

Project prototypes due today Project final reports due December 5th HW4 due November 5th HW5 out November 5th and due November 19th Final exam scheduled
- Monday, December 16th from 10:10 to noon in TBD

CSE477 L17 Static Sequential Logic.37

Irwin&Vijay, PSU, 2002