Beruflich Dokumente
Kultur Dokumente
MOSFET I-Vs
Substrate
Channel
Drain
Insulator
Gate
Operation of a transistor
V
SG
> 0
n type operation
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
More
electrons
Source
V
SD
V
SG
Some important equations in the
inversion regime (Depth direction)
V
T
= |
ms
+ 2
B
+
ox
W
dm
= \[2c
S
(2
B
)/qN
A
]
Q
inv
= -C
ox
(V
G
- V
T
)
ox
= Q
s
/C
ox
Q
s
= qN
A
W
dm
V
T
= |
ms
+ 2
B
+ \[4c
S
B
qN
A
]/C
ox
Substrate
Channel
Drain
Insulator
Gate
Source
x
ECE 663
MOSFET Geometry
x
y
z
L
Z
S
D
V
G
V
D
ECE 663
How to include y-dependent potential
without doing the whole problem over?
ECE 663
Assume potential V(y) varies slowly along
channel, so the x-dependent and y-dependent
electrostats are independent
(GRADUAL CHANNEL APPROXIMATION)
i.e.,
Ignore E
x
/y
Potential is separable in
x and y
ECE 663
How to include y-dependent potentials?
S
= 2
B
+ V(y)
V
G
=
S
+ \[2c
S
S
qN
A
]/C
ox
Need V
G
V(y) > V
T
to invert
channel at y (V increases
threshold)
Since V(y) largest at drain end, that
end reverts from inversion to
depletion first (Pinch off)
SATURATION [V
DSAT
= V
G
V
T
]
j = qn
inv
v = (Q
inv
/t
inv
)v
I = jA = jZt
inv
= ZQ
inv
v
ECE 663
So current:
Q
inv
= -C
ox
[V
G
V
T
- V(y)]
v
= -
eff
dV(y)/dy
ECE 663
So current:
I =
eff
ZC
ox
[V
G
V
T
- V(y)]dV(y)/dy
I =
eff
ZC
ox
[(V
G
V
T
)V
D
- V
D
2
/2]/L
Continuity implies Idy = IL
ECE 663
But this current behaves like a parabola !!
I
D
V
D
I
D
sat
V
D
sat
I =
eff
ZC
ox
[(V
G
V
T
)V
D
- V
D
2
/2]/L
We have assumed inversion in our model (ie, always above pinch-off)
So we just extend the maximum current into saturation
Easy to check that above current is maximum for V
Dsat
= V
G
- V
T
Substituting, I
Dsat
= (C
ox
eff
Z/2L)(V
G
-V
T
)
2
Whats Pinch off?
0
0
0
0
V
G
V
G
Now add in the drain voltage to drive a current. Initially you get
an increasing current with increasing drain bias
0
V
D
V
G
V
G
When you reach V
Dsat
= V
G
V
T
, inversion is disabled at the drain
end (pinch-off), but the source end is still inverted
The charges still flow, just that you cant draw more current
with higher drain bias, and the current saturates
Square law theory of MOSFETs
I =
eff
ZC
ox
[(V
G
V
T
)V
D
- V
D
2
/2]/L, V
D
< V
G
- V
T
I =
eff
ZC
ox
(V
G
V
T
)
2
/2L, V
D
> V
G
- V
T
J = qnv
n ~ C
ox
(V
G
V
T
)
v ~
eff
V
D
/L
ECE 663
Ideal Characteristics of n-channel
enhancement mode MOSFET
ECE 663
Drain current for REALLY small V
D
( )
( ) | |
( )
T G D
D T G i n D
D D T G i n D
V V V
V V V C
L
Z
I
V V V V C
L
Z
I
<<
~
(
2
2
1
Linear operation
Channel Conductance:
) (
T G i n
V
D
D
D
V V C
L
Z
V
I
g
G
=
c
c
Transconductance:
D i n
V
G
D
m
V C
L
Z
V
I
g
D
=
c
c
ECE 663
In Saturation
Channel Conductance:
Transconductance:
( )
2
2
T G i n D
V V C
L
Z
sat I =
0 =
c
c
G
V
D
D
D
V
I
g
( )
T G i n
V
G
D
m
V V C
L
Z
V
I
g
D
=
c
c
ECE 663
Equivalent Circuit Low Frequency AC
Gate looks like open circuit
S-D output stage looks like current source with channel
conductance
g m d D
G
V
G
D
D
V
D
D
D
v g v g i
V
V
I
V
V
I
I
D G
+ =
o
c
c
+ o
c
c
= o
ECE 663
Input stage looks like capacitances gate-to-source(gate) and
gate-to-drain(overlap)
Output capacitances ignored -drain-to-source capacitance
small
Equivalent Circuit Higher Frequency AC
ECE 663
Input circuit:
Input capacitance is mainly gate capacitance
Output circuit:
( )
g gate g gd gs in
v fC j v C C j i t ~ + e = 2
g m out
v g i ~
gate
m
in
out
fC
g
i
i
t
=
2
D i n
V
G
D
m
V C
L
Z
V
I
g
D
=
c
c
=
t
=
t
=
ZL C C
i gate
=
ECE 663
Maximum Frequency (not in saturation)
2
max
2 L
V
f
D n
t
=
L V v
v L
D /
/
1
max
e
=
=
(Inverse transit time)
ECE 663
Switching Speed, Power Dissipation
t
on
= C
ox
ZLV
D
/I
ON
Trade-off: If C
ox
too small, C
s
and C
d
take over and you lose
control of the channel potential (e.g. saturation)
(DRAIN-INDUCED BARRIER LOWERING/DIBL)
If C
ox
increases, you want to make sure you dont control
immobile charges (parasitics) which do not contribute to
current.
ECE 663
Switching Speed, Power Dissipation
P
dyn
= C
ox
ZLV
D
2
f
P
st
= I
off
V
D
ECE 663
CMOS
NOT gate
(inverter)
ECE 663
CMOS
NOT gate
(inverter)
Positive gate turns nMOS on
V
in
= 1 V
out
= 0
ECE 663
CMOS
NOT gate
(inverter)
Negative gate turns pMOS on
V
in
= 0 V
out
= 1
ECE 663
So what?
If we can create a NOT gate
we can create other gates
(e.g. NAND, EXOR)
ECE 663
So what?
Ring Oscillator
ECE 663
So what?
More importantly, since one is open and one is shut at steady
state, no current except during turn-on/turn-off
Low power dissipation
ECE 663
Getting the inverter output
Gain
ON
OFF
ECE 663
0 =
c
c
G
V
D
D
D
V
I
g
( )
T G i n
V
G
D
m
V V C
L
Z
V
I
g
D
=
c
c
\
|
| =
c
+ + =
i
BS B A s
B FB T
C
V qN
V V
) 2 ( 2
2
+ c
+ + =
ECE 663
Threshold Voltage Control
Substrate Bias:
i
BS B A s
B FB T
C
V qN
V V
) 2 ( 2
2
+ c
+ + =
( )
B BS B
i
A s
T
BS T BS T T
V
C
qN
V
V V V V V
+
c
= A
= = A
2 2
2
) 0 ( ) (
ECE 663
Threshold Voltage Control-substrate bias
ECE 663
It also affects the I-V
V
G
The threshold voltage is increased due to the depletion region
that grows at the drain end because the inversion layer shrinks
there and cant screen it any more. (W
d
> W
dm
)
Q
inv
= -C
ox
[V
G
-V
T
(y)], I = -
eff
ZQ
inv
dV(y)/dy
V
T
(y) = + 2c
s
qN
A
/C
ox
= 2
B
+ V(y)
ECE 663
It also affects the I-V
IL =
eff
ZC
ox
[V
G
(2
B
+V) - 2c
s
qN
A
(2
B
+V)/C
ox
]dV
I = (Z
eff
C
ox
/L)[(V
G
2
B
)V
D
V
D
2
/2
-22c
s
qN
A
{(2
B
+V
D
)
3/2
-(2
B
)
3/2
}/3C
ox
]
ECE 663
We can approximately include this
Include an additional charge term from the
depletion layer capacitance controlling V(y)
Q = -C
ox
[V
G
-V
T
]+(C
ox
+ C
d
)V(y)
where C
d
= c
s
/W
dm
Q = -C
ox
[V
G
V
T
- MV(y)], M = 1 + C
d
/C
ox
I
D
= (Z
eff
C
ox
/L)[(V
G
-V
T
- MV
D
/2)V
D
]
ECE 663
Comparison between different models
Square Law Theory
Body Coefficient
Bulk Charge Theory
Still not good below threshold or above saturation
ECE 663
Mobility
Drain current model assumed constant mobility in channel
Mobility of channel less than bulk surface scattering
Mobility depends on gate voltage carriers in inversion
channel are attracted to gate increased surface scattering
reduced mobility
ECE 663
Mobility dependence on gate voltage
) ( 1
0
T G
V V u +
=
ECE 663
Sub-Threshold Behavior
For gate voltage less than the threshold weak inversion
Diffusion is dominant current mechanism (not drift)
L
L n o n
qAD
y
n
qAD A J I
n n D D
) ( ) (
~
c
c
= =
kT V q
i
kT q
i
D B s
B s
e n L n
e n n
/ ) (
/ ) (
) (
) 0 (
=
=
ECE 663
Sub-threshold
( )
kT q kT qV
kT
i n
D
s D
B
e e
L
e n qAD
I
/ /
/
1
=
We can approximate
s
with V
G
-V
T
below threshold since all
voltage drops across depletion region
( )
( ) kT V V q kT qV
kT
i n
D
T G D
B
e e
L
e n qAD
I
/ /
/
1
~
Sub-threshold current is exponential function of applied gate voltage
Sub-threshold current gets larger for smaller gates (L)
ECE 663
Subthreshold Characteristic
( ) ( )
G D
V I
S
c c
log
1
Subthreshold Swing
Tunneling transistor
Band filter like operation
J Appenzeller et al, PRL 04
Ghosh, Rakshit, Datta
(Nanoletters, 2004)
(S
conf
)
min
=2.3(k
B
T/e).(et
ox
/m)
Hodgkin and Huxley, J. Physiol. 116, 449 (1952a)
Subthreshold slope = (60/Z) mV/decade
Much of new research depends on reducing S !
Much of new research depends on reducing S !
Increase q by collective motion (e.g. relay)
Ghosh, Rakshit, Datta, NL 03
Effectively reduce N through interactions
Salahuddin, Datta
Negative capacitance
Salahuddin, Datta
Non-thermionic switching (T-independent)
Appenzeller et al, PRL
Nonequilibrium switching
Li, Ghosh, Stan
Impact Ionization
Plummer
ECE 663
More complete model sub-threshold to
saturation
Must include diffusion and drift currents
Still use gradual channel approximation
Yields sub-threshold and saturation behavior for long
channel MOSFETS
Exact Charge Model numerical integration
} }
|
|
.
|
\
|
|
c
=
| |
D s
B
V
p
p
V
D
n s
D
p
n
V F
e
L L
Z
I
0
0
0
, ,
ECE 663
Exact Charge Model (Pao-Sah)
Long Channel MOSFET
http://www.nsti.org/Nanotech2006/WCM2006/WCM2006-BJie.pdf
ECE 663