Flip Flops

Introduction
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A flip-flop is a synchronised bistable device. The output changes is stated only at a specified point on a triggering input called the clock which is designed as a controlled input. An edge-triggered flip-flop changes its state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse. Flip-flop is used as a memory device, counter and etc. Types of flip-flops SR Flip-flop D Flip-flop JK Flip-flop T Flip-flop

SR Flip - Flop

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a. Symbol
S Clock Q

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b. Circuit diagram
S Q Clock

Q R

SR Flip - Flop
c. Truth table
Input
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Output
Clock

S 0 0 1 1

R 0 1 0 1

Q Q0 0 1 ?

Q Q0 1 0 ?

Comments

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No change Reset Set Invalid

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d. Timing diagram
Clock S R Q Q No change Reset 1 2 3 4 5 6

Set

Reset

Set

Set

D Flip - Flops
D Flip-flop is useful when a single data bit (1 or 0) is to be stored - Formed from an SR flip-flop and an inverter
-

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a. Symbol
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Q Q

S R

Q Q

Clock

D Flip - Flops

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b. Circuit diagram D
Clock
Q Q

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D Flip - Flop
c. Truth table
Output
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Statement Q 1 0 Reset Set

D 0 1

Clock

Q 0 1

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d. Timing diagram
Clock 1 2 3 4

Set

Reset

Set

Reset

JK Flip - Flop
- Versatile

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and perhaps the most widely used type of flip-flop. - The functioning of the JK flip-flop is identical to that of the SR flipflop except that the JK flip-flop has no invalid state. a. Symbol
Clock J Q

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b. Circuit diagram
J Q

Clock

Q
K

JK Flip - Flop

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c. Truth table
J 0 0 1 1 Input K 0 1 0 1 Clock Output Q Q Q0 Q0 0 1 ? 1 0 ? Statement No Changes Reset Set Toggle

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JK Flip-Flops
d. Timing diagrams
Clock
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Toggle

No Change

Reset

Set

Set

T Flip - Flop
- Formed from a JK flip-flop with both inputs are tied together. a. Symbol
Q T HOME J Clock Q K Q

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Clock

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b. Circuit diagram
T Q Clock

T Flip-Flop
c. Truth table
Input T Clock 0 1 Output Q Q Q0 Q0 Q0 Q0 Statement

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No Changes Toggle

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d. Timing diagrams
Clock T Toggle No Changes 1 2 3 4 5

No Changes Toggle Toggle

Applications

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* Counter Shift Register Memory Device Timer 555

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