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  • Synthesis

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    anjugadu
    44 Ansichten13 Seiten
    Logic synthesis is the process of translating a design description written in HDL into a gate-level netlist based on optimization constraints and a technology library. It involves mapping the HDL description to a Boolean network, optimizing the network through logic minimization, and mapping the optimized network onto an equivalent cell network from the technology library. The optimization process occurs at the RTL, logic, and gate levels to minimize area, delay, or other objectives specified in the design constraints.

    Originalbeschreibung:

    HDL SYNTHESIS

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    Logic synthesis is the process of translating a design description written in HDL into a gate-level netlist based on optimization constraints and a technology library. It involves mapping the HDL description to a Boolean network, optimizing the network through logic minimization, and mapping the optimized network onto an equivalent cell network from the technology library. The optimization process occurs at the RTL, logic, and gate levels to minimize area, delay, or other objectives specified in the design constraints.

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    © All Rights Reserved
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    44 Ansichten13 Seiten

    Synthesis

    Hochgeladen von

    anjugadu
    Logic synthesis is the process of translating a design description written in HDL into a gate-level netlist based on optimization constraints and a technology library. It involves mapping the HDL description to a Boolean network, optimizing the network through logic minimization, and mapping the optimized network onto an equivalent cell network from the technology library. The optimization process occurs at the RTL, logic, and gate levels to minimize area, delay, or other objectives specified in the design constraints.

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    © All Rights Reserved
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    Markieren Sie unangemessene Inhalte
    von 13

    What is Synthesis ?

    Logic Synthesis is the process of translating a design description written in vhdl / verilog HDL into gates from the technology library based on user specified optimization constraints.

    *Synthesis is the automatic process of connecting a higher


    level of abstraction to a lower level of abstraction .

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    + Mapping

    HDL Source

    + Mapping Generic ( GTECH)

    Target Technology

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    Logic Synthesis
    Given
    a Boolean network - a set of Boolean expressions and a target library

    By optimizing
    Boolean expressions by logic minimization procedures and

    Map
    the Boolean network onto an equivalent cell network

    Binding
    the nodes in the network to the gates in the target library

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    S
    Y N T E S I

    Informal Description

    translate

    UnOptimised Boolean description


    optimize

    Optimized boolean description

    L
    O W
    4/16/2014 BALAJI, PROF,JNTUKUCEV

    Mapping to gates

    Informal (RTL) Description Specification In HDL

    SYNTHESIS CONSTRAINTS

    TECHNOLOGY LIBRARY

    SYNTHESIS

    netlist
    4/16/2014 BALAJI, PROF,JNTUKUCEV 5

    Optimization
    Optimization is done at three intermediate levels in the synthesis converting HDL code to gate level net list
    RTL (Register Transfer Level) Level optimization Logic Level optimization Gate Level optimization

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    RTL level optimization


    Here code related processing is optimized such as Expansion : sub programs in line are expanded Constant folding constants are folded to gather ex: A+2+3 becomes A+5 loop unrolling Dead code removal Bit minimization
    4/16/2014 BALAJI,ASSOC.PROF,VNRVJIET 7

    Logic level optimization


    The combinational logic part of the circuit is optimized using boolean equations according to the rules of boolean logic such as

    Flattening :is conversion of multiple boolean equations into a two level sum of products form. factoring is the process of adding intermediate terms
    4/16/2014 BALAJI, PROF,JNTUKUCEV 8

    OPTIMIZATION TECHNIQUE
    * FLATTENING
    A = B and C , B = Y or Z, C = Q or W after flattening A = (Y and Q) or (Y and W) or (Z and Q) or (Z and c) [removes two variables A,B]

    * FACTORING
    X = A and B or A and D Y= Z or Q after factoring X= A and Q Y = Z or Q
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    where Q = B or D

    NOTES:
    Flattening :is conversion of multiple boolean equations into a two level sum of products form. Factoring is the process of adding intermediate terms AMONG THESE TWO, THE IDEAL CASE IS ONE WHICH CRITICAL PATH WAS FLATTEND FOR SPEED AND REST DESIGN FACTORED FOR SMALL AREA AND FANOUT

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    10

    Gate level optimization


    This is the process of optimizing area of logic by replacing the cells with less area /few cells without altering the functionality The optimization will be mainly with respect to minimal chip area irrespective of timing delays maximal speed irrespective of area

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    11

    Technology Mapping
    Map the Boolean factors to the cells of the library(tech library] Methods
    Graph matching Tree matching Mapping based on string matching Layout driven technology mapping

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    12

    Constraints:
    * Timing constraints * Area constraints * Power constraints

    4/16/2014

    BALAJI, PROF,JNTUKUCEV

    13

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