EE603 CMOS INTEGRATED CIRCUIT DESIGN

Static CMOS inverter

Azman Bin Mat Hussin

Outline
CMOS inverter switch model CMOS inverter properties CMOS inverter loads line CMOS inverter voltage transfer characteristic The switch model of dynamic behavior of static CMOS inverter

CMOS INVERTER

CMOS VLSI Design

Slide 2

CMOS Inverter Transistor level & layout

N Well

VDD

VDD 2l

PMOS

PMOS In Out
In

Contacts

Out Metal 1

NMOS

Polysilicon

NMOS GND Circuits and Layout CMOS VLSI Design Slide 3

Two Inverters
Share power and ground Abut cells
VDD
Connect in Metal

Circuits and Layout

CMOS VLSI Design

Slide 4

CMOS Switch Characteristic

Switch In Series
INPUT
Truth Table S1

S1 OFF OFF

S2 OFF ON OFF ON

PATH?

S2

ON ON
OUTPUT

Circuits and Layout

CMOS VLSI Design

Slide 5

CMOS Switch Characteristic

Switch In Series
INPUT

Truth Table (OFF/ON=0/1)

S1

S1 OFF OFF

S2 OFF ON

PATH? NO NO

S2

ON ON
OUTPUT

OFF ON
What Function ??

NO YES

Circuits and Layout

CMOS VLSI Design

Slide 6

CMOS Switch Characteristic

Switch In Series INPUT

Truth Table (OFF/ON=0/1) S1

S1 0

S2 0

PATH? 0

S2

OUTPUT
Circuits and Layout

Function = ??
CMOS VLSI Design Slide 7

CMOS Switch Characteristic

Switch In Series
INPUT Truth Table (OFF/ON=0/1)

S1

S1 0 0

S2 0 1

PATH? 0 0

S2

OUTPUT
Circuits and Layout

Function = ??
CMOS VLSI Design Slide 8

CMOS Switch Characteristic

Switch In Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0 0

S2 0 1 0

PATH? 0 0 0

S2

OUTPUT
Circuits and Layout

Function = ??
CMOS VLSI Design Slide 9

CMOS Switch Characteristic

Switch In Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0 0

S2 0 1 0 1

PATH? 0 0 0 1

S2

1 1
OUTPUT

Function = Logic AND

CMOS VLSI Design Slide 10

Circuits and Layout

CMOS Switch Characteristic

Switch In Parallel
INPUT
Truth Table

S1 OFF
S1 S2

S2 OFF ON
OFF ON

PATH? NO YES
YES YES

OFF
ON ON

OUTPUT
Circuits and Layout CMOS VLSI Design Slide 11

CMOS Switch Characteristic

Switch In Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0

PATH? 0

OUTPUT
Circuits and Layout

Function =??
CMOS VLSI Design Slide 12

CMOS Switch Characteristic

Switch In Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1

PATH? 0 1

OUTPUT
Circuits and Layout

Function =??
CMOS VLSI Design Slide 13

CMOS Switch Characteristic

Switch In Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1 0

PATH? 0 1 1

0 1

OUTPUT
Circuits and Layout

Function =??
CMOS VLSI Design Slide 14

CMOS Switch Characteristic

Switch In Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1 0

PATH? 0 1 1

0 1

1
OUTPUT
Circuits and Layout

1
Function = Logic OR

CMOS VLSI Design

Slide 15

CMOS TRANSISTOR
Source Gate Drain pMOS

Drain Gate Source nMOS

Circuits and Layout

Complementary MOS P-channel MOS (pMOS) N-channel MOS (nMOS) pMOS P-type source and drain diffusions N substrate Mobility by holes nMOS N-type source and drain diffusions P substrate Mobility by electrons
CMOS VLSI Design Slide 16

CMOS Signal Transfer Property

Source Gate Drain pMOS

Gate 0 1

Path Closed Open

Transmits 1 well Transmits 0 poorly

Drain Gate

Gate 0
Source
nMOS

Path Open Closed

Transmits 0 well Transmits 1 poorly
Slide 17

Circuits and Layout

CMOS VLSI Design

High Impedance
When a path exists
Impedance is low to allow ample flow of current
Source Closed

Gate=1
Drain

<< 10K

When no path
Impedance is high allowing almost no current flow between two terminals
Circuits and Layout

Gate=0 Source Open

>> 100M

Drain

CMOS VLSI Design

Slide 18

Switch Model of NMOS Transistor

| VGS |

Gate

Source (of carriers)

Drain (of carriers)

Open (off) (Gate = 0)

Closed (on) (Gate = 1)

Ron

| VGS | < | VT |
Circuits and Layout

| VGS | > | VT |
CMOS VLSI Design Slide 19

Switch Model of PMOS Transistor

| VGS |

Gate

Source (of carriers)

Drain (of carriers)

Open (off) (Gate = 1)

Closed (on) (Gate = 0)

Ron

| VGS | > | VDD | VT | |

Circuits and Layout

| VGS | < | VDD |VT| |

CMOS VLSI Design Slide 20

CMOS Inverter: Switch Model of Dynamic Behavior

VDD VDD

Rp

Vout Rn

Vout

VOL = 0 VOH = VDD VM = f(Rn, Rp)

Vin 5 VDD
Circuits and Layout

Vin 5 0
CMOS VLSI Design Slide 21

CMOS Inverter: Transient Response

Gate response time is determined by the time to charge CL

through Rp (discharge CL through Rn)

DD

VDD

Rp Vout CL Rn

Vout
CL

Vin 5 0
Circuits and Layout

Vin 5 VDD
CMOS VLSI Design

(a) Low-to-high

(b) High-to-low

Slide 22

CMOS INVERTER AS SWITCH

SYMBOL
INPUT A = LOGIC 1
1. 2.

TRUTH TABLE

INPUT A = LOGIC 0
1. 2.

3.

NMOS is ON, PMOS is OFF. NMOS will transfer logic 0 (GND) to the output. Output Y = Logic 0

3.

PMOS is ON, NMOS is OFF. PMOS will transfer logic 1 (VDD) to the output. Output Y = Logic 1

Circuits and Layout

CMOS VLSI Design

Slide 23

important properties of static CMOS

1. The high and low output levels equal VDD and GND, respectively 2. The logic levels are not dependent upon the relative device sizes, so that the transistors can be minimum size.

3. In steady state, there always exists a path with finite resistance between the output and either VDD or GND. Typical values of the output resistance are in kW range.
4. The input resistance of the CMOS inverter is extremely high, as the gate of an MOS transistor is a virtually perfect insulator and draws no dc input current
Circuits and Layout CMOS VLSI Design Slide 24

Voltage Transfer Characteristic

Circuits and Layout

CMOS VLSI Design

Slide 25

Summary of transistor operation

NMOS transistor PMOS transistor

Circuits and Layout

CMOS VLSI Design

Slide 26

CMOS inverter load lines

The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by superimposing the current characteristics of the NMOS and the PMOS. Such a graphical construction is traditionally called a load-line plot. It requires that the I-V curves of the NMOS and PMOS devices are transformed onto a common coordinate set. We have selected the input voltage Vin, the output voltage Vout and the NMOS drain current IDN as the variables of choice. The PMOS I-V relations can be translated into this variable space by the following relations

Circuits and Layout

CMOS VLSI Design

Slide 27

CMOS inverter load lines

The PMOS I-V relations can be translated into this variable space by the following relations

The load-line curves of the PMOS device are obtained by a mirroring around the xaxis and a horizontal shift over VDD. This procedure is outlined in Figure below, where the subsequent steps to adjust the original PMOS I-V curves to the common coordinate set Vin, Vout and IDn are illustrated.

Circuits and Layout

CMOS VLSI Design

Slide 28

CMOS inverter load lines

IDn V in = V DD -VGSp IDn = - IDp V out = VDD -VDSp

V out IDp Vin=0 V in=3 IDn IDn Vin=0 Vin=3

V DSp VGSp=-2 VGSp=-5 Vin = V DD-VGSp IDn = - IDp

V DSp

Vout

Vout = V DD-VDSp

Transforming PMOS I-V characteristic to a common coordinate set (assuming VDD = 2.5 V).
CMOS VLSI Design Slide 29

Circuits and Layout

DC transfer characteristics

Circuits and Layout

CMOS VLSI Design

Slide 30

CMOS Inverter Load Characteristics

ID n Vin = 0 Vin = 2.5

PMOS

Vin = 0.5

Vin = 2

NMOS

Vin = 1 Vin = 1.5 Vin = 1.5 Vin = 2 Vin = 2.5

Vin = 1.5 Vin = 1 Vin = 1 Vin = 0.5 Vin = 0

Vout Figure 2: Load curves for NMOS and PMOS transistors of the static CMOS inverter ( VDD = 2.5 V). The dots represent the dc operation points for various input voltages
Circuits and Layout CMOS VLSI Design Slide 31

CMOS Inverter Load Characteristics

The resulting load lines are plotted in Figure 2 For a dc operating points to be valid, the currents through the NMOS and PMOS devices must be equal. Graphically, this means that the dc points must be located at the intersection of corresponding load lines. A number of those points (for Vin = 0, 0.5, 1, 1.5, 2, and 2.5 V) are marked on the graph. As can be observed, all operating points are located either at the high or low output levels. The VTC of the inverter hence exhibits a very narrow transition zone. This results from the high gain during the switching transient, when both NMOS and PMOS are simultaneously on, and in saturation. In that operation region, a small change in the input voltage results in a large output variation. All these observations translate into the VTC

Circuits and Layout

CMOS VLSI Design

Slide 32

CMOS Inverter VTC

2.5 2
NMOS off PMOS res

VDD
NMOS sat PMOS res

A
Vout (V)
1.5 1 0.5 0 0 0.5

B C
NMOS sat PMOS sat

Vout CL

NMOS res PMOS sat

NMOS res PMOS off

1.5 Vin (V)

2.5

Circuits and Layout

CMOS VLSI Design

Slide 33

Complete voltage transfer characteristic VTC

NMOS in sat PMOS in non sat

NMOS off PMOS in non sat

Drain current IDS

NMOS in sat PMOS in sat

Vin=4V Vin=3V Vin=2V Vin=1V Vout = VDS VCC

NMOS in non sat PMOS in sat

NMOS in nonsat PMOS off

Circuits and Layout

CMOS VLSI Design

Slide 34