Unit-5

Microcomputer

microcomputer

What is Microcomputer?

A microcomputer is a general purpose system; i.e.; the system is organized in such a way that it can perform a large variety of computation.

microcomputer

How to achieve Objective

Each computation is represented by a sequence of instructions (a program )that is stored in a read write memory and is executed by microcomputer. The execution of instructions produces transformations on the data.

microcomputer

Basic components of a microcomputer

Processor

Memory Subsystem

I/O Subsystem

I/O devices

microcomputer

A microcomputer consist of three subsystems:

A Processor A memory subsystem An input/output (I/O) subsystem

microcomputer

Processor
It is the computing engine of the microcomputer; it executes the sequence of instructions i.e.. the program. it is also known as Central Processing Unit.

microcomputer

Memory Subsystem
It stores the program as well as the data used by the program. The memory is divided into locations, such as bytes and words; these locations are identified by their address.

microcomputer

Memory operations
Read: the processor provides the address and receives the data read from the location addressed. Write: the processor provides both address and the data to be stored at the corresponding location.

microcomputer

I/O subsystem
It contains the interface to devices that allow transferring data input to/ from the computer.

microcomputer

Specification of memory subsystem

Addr(24) data(32) Length Read Write Enable Rdy

microcomputer

10

Memory subsystem signals specification

Enable: enable signal has to be active for the system to be active Read/Write: the subsystem responds to an event when one of these control signals are active. Length: it tells the size of an operand. length=0 if size is in bytes 1 if size is in words
microcomputer 11

Memory subsystem signals specification

Addr: the address of the memory location being accessed. Data: data is transferred through signal data. Rdy: it tells the memory operation completion.
Rdy=0 if operation is in progress 1 if operation completes
microcomputer 12

How the operation would be performed

Read 0
0 1

Write 0
1 0

Enable 0
1 1

Operation No operation Write Access Read Access

13

microcomputer

Entity declaration of Memory subsystem

1. LIBRARY ieee; 2. USE ieee.std_logic_1164.all; 3. USE WORK.comp_pkg.ALL; 4. ENTITY Memory IS 5. PORT (Addr : IN MAddrT ; -- memory address bus 6. Length : IN STD_LOGIC; -- byte/word operand 7. Rd, Wr : IN STD_LOGIC; -- access control signals 8. Enable : IN STD_LOGIC; -- enable signal 9. Rdy : OUT STD_LOGIC; -- access completion signal 10. Data : INOUT WordT ); -- memory data bus 11. END Memory;
microcomputer 14

Specification of I/O subsystem

Addr(11) data(32) Length Read Write Enable Rdy

microcomputer

15

Entity declaration of I/O subsystem

1. LIBRARY ieee; 2. USE ieee.std_logic_1164.all; 3. USE WORK.comp_pkg.ALL; 4. ENTITY IO IS 5. PORT (Addr : IN IOAddrT ; -- I/O address bus 6. Length : IN STD_LOGIC; -- byte/word control 7. Rd, Wr : IN STD_LOGIC; -- I/O access control 8. Enable : IN STD_LOGIC; -- I/O enable control 9. Rdy : OUT STD_LOGIC; -- I/O completion signal 10. Data : INOUT WordT ); -- I/O data bus 11. END IO;
microcomputer 16

Arithmetic Logic Unit (ALU)

Definition: The arithmetic logic unit (ALU) is a digital circuit that calculates an arithmetic operation (like an addition, subtraction, etc.) and logic operations (like an Exclusive Or) between two numbers. The ALU is a fundamental building block of the central processing unit of a computer.

microcomputer

17

Entity Declaration of ALU

1. library IEEE; 2. use IEEE.STD_LOGIC_1164.all; 3. use work.pack.all; 4. entity alu is 5. port( 6. a : in STD_LOGIC_VECTOR( 15 downto 0); 7. b : in STD_LOGIC_VECTOR( 15 downto 0); 8. sel : in opcode; 9. c : out STD_LOGIC_VECTOR( 15 downto 0) 10. ); 11. end alu;
microcomputer 18

Architecture of ALU
architecture alu of alu is begin aluproc: process (a, b, sel) begin

case sel is
when alupass => c <= a after 1 ns; when andOp => c <= (a and b) after 1 ns;
microcomputer 19

Architecture..
when orOp => c <= a or b after 1 ns; when xorOp => c <= a xor b after 1 ns; when notOp => c <= not a after 1 ns;

microcomputer

20

Architecture..
when plus => c <= a + b after 1 ns; when alusub => c <= a - b after 1 ns; when inc => c <= a + "0000000000000001" after 1 ns;

microcomputer

21

Architecture..
when dec => c <= a - "0000000000000001" after 1 ns; when zero => c <= "0000000000000000" after 1 ns; when others => c <= "0000000000000000" after 1 ns;

end case;
end process; end alu;
microcomputer 22

Package( work.pack.all)
Package used in ALU library IEEE; use IEEE.STD_LOGIC_1164.all; package pack is type opcode is (alupass ,andop ,orop ,xorop ,notop ,plus ,alusub ,inc ,dec ,zero); function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector; function "-"(opd1,opd2:std_logic_vector(15 downto 0))return std_logic_vector; end package;
microcomputer 23

Package Body(work.pack.all)
package body pack is function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector is variable sum:std_logic_vector(15 downto 0); variable carry:std_logic:='0'; begin for i in 15 downto 0 loop sum(i):= opd1(i) xor opd2(i)xor carry; carry:= (opd1(i) and opd2(i))or(opd2(i) and carry)or (opd1(i) and carry); end loop; return sum; end function;
microcomputer 24

Package Body(work.pack.all)..
function "-"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector is variable diff:std_logic_vector( 15 downto 0); variable borrow:std_logic:='0'; begin for i in 15 downto 0 loop diff(i):= opd1(i) xor opd2(i)xor borrow; borrow:= ( (not opd1(i)) and borrow)or((not opd1(i))and opd2(i) )or (opd2(i) and borrow); end loop; \ return diff; end function; end pack;

microcomputer

25

Simulation

microcomputer

26